mirror of https://github.com/efabless/caravel.git
107 lines
2.8 KiB
YAML
107 lines
2.8 KiB
YAML
- status: 0 - openlane design prep
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runtime_s: 1.79
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runtime_ts: 0h0m1s790ms
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- status: 1 - synthesis - yosys
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runtime_s: 1.24
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runtime_ts: 0h0m1s241ms
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- status: 2 - sta - openroad
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runtime_s: 0.43
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runtime_ts: 0h0m0s428ms
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- status: 3 - floorplan initialization - openroad
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runtime_s: 0.55
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runtime_ts: 0h0m0s552ms
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- status: 4 - ioplace - openroad
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runtime_s: 0.42
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runtime_ts: 0h0m0s422ms
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- status: 5 - tap/decap insertion - openroad
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runtime_s: 0.44
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runtime_ts: 0h0m0s444ms
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- status: 6 - pdn generation - openroad
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runtime_s: 0.46
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runtime_ts: 0h0m0s457ms
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- status: 7 - global placement - openroad
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runtime_s: 0.57
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runtime_ts: 0h0m0s570ms
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- status: 8 - detailed placement - openroad
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runtime_s: 0.47
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runtime_ts: 0h0m0s470ms
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- status: 9 - detailed placement - openroad
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runtime_s: 0.47
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runtime_ts: 0h0m0s472ms
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- status: 11 - write verilog - openroad
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runtime_s: 0.42
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runtime_ts: 0h0m0s418ms
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- status: 11 - global routing - openroad
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runtime_s: 0.52
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runtime_ts: 0h0m0s517ms
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- status: 12 - fill insertion - openroad
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runtime_s: 0.48
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runtime_ts: 0h0m0s483ms
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- status: 13 - detailed_routing - openroad
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runtime_s: 1.81
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runtime_ts: 0h0m1s806ms
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- status: 14 - wire lengths - openlane
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runtime_s: 0.26
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runtime_ts: 0h0m0s262ms
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- status: 15 - parasitics extraction - openroad
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runtime_s: 0.46
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runtime_ts: 0h0m0s462ms
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- status: 16 - sta - openroad
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runtime_s: 1.54
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runtime_ts: 0h0m1s542ms
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- status: 17 - parasitics extraction - openroad
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runtime_s: 0.45
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runtime_ts: 0h0m0s454ms
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- status: 18 - sta - openroad
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runtime_s: 1.55
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runtime_ts: 0h0m1s551ms
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- status: 19 - parasitics extraction - openroad
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runtime_s: 0.45
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runtime_ts: 0h0m0s447ms
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- status: 20 - sta - openroad
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runtime_s: 1.54
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runtime_ts: 0h0m1s536ms
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- status: 21 - sta - openroad
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runtime_s: 0.39
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runtime_ts: 0h0m0s392ms
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- status: 22 - ir drop report - openroad
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runtime_s: 0.42
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runtime_ts: 0h0m0s424ms
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- status: 23 - gdsii - magic
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runtime_s: 1.38
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runtime_ts: 0h0m1s383ms
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- status: 24 - gdsii - klayout
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runtime_s: 0.44
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runtime_ts: 0h0m0s438ms
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- status: 25 - xor - klayout
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runtime_s: 0.41
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runtime_ts: 0h0m0s415ms
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- status: 26 - spice extraction - magic
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runtime_s: 0.44
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runtime_ts: 0h0m0s441ms
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- status: 28 - write verilog - openroad
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runtime_s: 0.4
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runtime_ts: 0h0m0s403ms
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- status: 28 - write powered verilog - openlane
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runtime_s: 0.52
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runtime_ts: 0h0m0s517ms
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- status: 29 - lvs - netgen
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runtime_s: 0.1
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runtime_ts: 0h0m0s102ms
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- status: 30 - drc - magic
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runtime_s: 1.18
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runtime_ts: 0h0m1s175ms
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- status: 31 - antenna check - openroad
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runtime_s: 0.46
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runtime_ts: 0h0m0s458ms
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- status: 32 - erc - circuit validity checker
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runtime_s: 0.13
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runtime_ts: 0h0m0s133ms
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---
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- status: routed
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runtime_s: 12.0
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runtime_ts: 0h0m12s0ms
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- status: flow completed
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runtime_s: 26.0
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runtime_ts: 0h0m26s0ms
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