mirror of https://github.com/efabless/caravel.git
151 lines
7.8 KiB
Plaintext
151 lines
7.8 KiB
Plaintext
Caravel management protect module
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------------------------------------
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The management protection module sits between the management SoC and
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the user project area on the Caravel chip. Its purpose is to maintain
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a protective buffer between the two, so that the user project area can
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be completely powered down without the management SoC dumping current
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into the user project circuits.
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The management protection module has two main functions:
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(1) Put tristate buffers on all outputs of the management SoC or
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housekeeping that connect to the user project wrapper pins, enabled
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with the 1/0 ("power good") state of the user project primary digital
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power supply (vccd1). This ensures that if the user project vccd1
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supply is not present and powered up to 1.8V, then the management SoC
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and housekeeping modules cannot generate current on these pins that
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would sink into the user project area.
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(2) AND all outputs of the user project that connect to the management
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SoC with memory-mapped enable bits. This allows the user project to
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leave any pins of the user project wrapper unconnected or tristated.
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Unconnected outputs of the user project wrapper going to the management
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SoC can be floating and will not affect operation of the chip as long
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as the respective enable bits are not set in the corresponding registers.
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Most of the protection circuitry is transparent to the user project, but
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the input enable registers must be set by the program running on the
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management SoC for the user project to be able to communicate data to the
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management SoC through either the logic analyzer interface or the wishbone
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bus interface.
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--------------------------------------------------------------------------
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Register name = reg_power_good
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Memory location = 0x2f000000
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Housekeeping SPI location = 0x1a
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | | | | | user1 | user2 | user1 | user2 |
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| 0x1a | | | | | vccd | vccd | vdda | vdda |
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| | | | | | power | power | power | power |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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bit 0: User 2 domain VDDA 3.3V supply (VDDA2) power good (read-only)
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value 0 = Supply VDDA2 is not present or under-voltage
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value 1 = Supply VDDA2 is present and powered (1.8V to 5.5V)
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bit 1: User 1 domain VDDA 3.3V supply (VDDA1) power good (read-only)
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value 0 = Supply VDDA1 is not present or under-voltage
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value 1 = Supply VDDA1 is present and powered (1.8V to 5.5V)
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bit 2: User 2 domain VCCD 1.8V supply (VCCD2) power good (read-only)
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value 0 = Supply VCCD2 is not present or under-voltage
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value 1 = Supply VCCD2 is present and 1.8V
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bit 3: User 1 domain VCCD 1.8V supply (VCCD1) power good (read-only)
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value 0 = Supply VCCD1 is not present or under-voltage
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value 1 = Supply VCCD1 is present and 1.8V
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--------------------------------------------------------------------------
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Register name = reg_la0_iena
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Memory location = 0x25000020 to 0x25000023 (32 bits or 4 bytes or 1 word)
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 31 | 30 | 29 | | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | la | la | la | | la | la | la | la |
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| | iena | iena | iena | ... | iena | iena | iena | iena |
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| | [31] | [30] | [29] | | [3] | [2] | [1] | [0] |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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Register name = reg_la1_iena
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Memory location = 0x25000024 to 0x25000027 (32 bits or 4 bytes or 1 word)
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 31 | 30 | 29 | | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | la | la | la | | la | la | la | la |
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| | iena | iena | iena | ... | iena | iena | iena | iena |
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| | [63] | [62] | [61] | | [35] | [34] | [33] | [32] |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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Register name = reg_la2_iena
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Memory location = 0x25000028 to 0x2500002b (32 bits or 4 bytes or 1 word)
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 31 | 30 | 29 | | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | la | la | la | | la | la | la | la |
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| | iena | iena | iena | ... | iena | iena | iena | iena |
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| | [95] | [94] | [93] | | [67] | [66] | [65] | [64] |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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Register name = reg_la3_iena
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Memory location = 0x2500002c to 0x2500002f (32 bits or 4 bytes or 1 word)
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 31 | 30 | 29 | | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | la | la | la | | la | la | la | la |
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| | iena | iena | iena | ... | iena | iena | iena | iena |
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| | [127] | [126] | [125 | | [99] | [98] | [97] | [96] |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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Note that the la_iena[] bits are not ports of the user project wrapper.
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They originate in the management SoC and terminate at the management
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protect module. They can only be set from the management SoC program.
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--------------------------------------------------------------------------
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Register name = reg_irq_enable
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Memory location = 0x2f000000
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | | | | | | irq 2 | irq 1 | irq 0 |
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| | | | | | | enable| enable| enable|
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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bit 0: IRQ 0 enable
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value 0 = User IRQ 0 from the user project is disabled
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and may be left unconnected or tristated.
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value 1 = User IRQ 0 from the user project is enabled and
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must be connected and driven.
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bit 1: IRQ 1 enable
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value 0 = User IRQ 1 from the user project is disabled
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and may be left unconnected or tristated.
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value 1 = User IRQ 1 from the user project is enabled and
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must be connected and driven.
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bit 2: IRQ 2 enable
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value 0 = User IRQ 2 from the user project is disabled
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and may be left unconnected or tristated.
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value 1 = User IRQ 2 from the user project is enabled and
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must be connected and driven.
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--------------------------------------------------------------------------
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Register name = reg_wb_enable
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Memory location = 0x2f000000
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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| | | | | | | | | wb |
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| | | | | | | | | enable|
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+------+-------+-------+-------+-------+-------+-------+-------+-------+
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bit 0: User wishbone enable
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value 0 = Wishbone signals wbs_dat_o and wbs_ack_o are
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disabled and may be left unconnected.
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value 1 = Wishbone signals wbs_dat_o and wbs_ack_o are
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enabled and must be connected and driven.
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