mirror of https://github.com/efabless/caravel.git
213 lines
12 KiB
Plaintext
213 lines
12 KiB
Plaintext
Caravel vs. Caravan
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----------------------------------------
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Caravel
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-------------------
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The Caravel chip user project can use the GPIO pins as analog signals,
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and this is the preferred method, as the GPIO pins have ESD protection
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on them.
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The restrictions on the use of GPIO pins for analog are the following:
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(1) The voltage range of the analog signal must be between VSSIO and
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VDDIO. On the demonstration board shipped with Caravel, VDDIO will
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be set to 3.3V from an external voltage regulator. However, VDDIO
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may be anywhere in the range of 1.8V to 5.5V.
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(2) The frequency range of the GPIO pads is 0 to 60MHz
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(3) Analog signals should be connected to the "analog_io" pins of the user
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project wrapper. This pin connects to the pad through a 120 ohm
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resistor, for ESD protection. However, it is recommended to place a
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diode close to the terminus in the user project circuit for any input
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signal that is not otherwise connected to diffusion, for additional
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ESD protection. This resistance should be included in system-level
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simulations.
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(4) When an analog signal is connected to a GPIO pad, the input and
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output buffers of the GPIO pad should be turned off, by setting the
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GPIO configuration to "GPIO_MODE_USER_STD_ANALOG" (see defs.h).
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Ideally, the buffers should be turned off by default on chip power-up,
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which is done by applying the same configuration in the "user_defines.v"
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file. This ensures that the digital buffers will never be turned on
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for those GPIOs.
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(5) Analog signals may not use GPIO 0 to 6 or GPIO 36 and 37. This prevents
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the critical signals such as debug, housekeeping SPI, and flash QSPI
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mode pins from being unable to operate due to a constant analog signal
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being present on the pad. Therefore there are up to 28 GPIO pins that
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can be used for analog signaling.
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Note that the signal names analog_io[27:0] are shifted relative to the
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GPIO pad names (mprj_io). So analog_io[0] connects to mprj_io[7], and
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so forth up to analog_io[27] which connects to mprj_io[34].
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Caravan
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-------------------
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In the case that a pin is needed that requires voltages above 5.5V, below
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0.0V, has a frequency higher than 60MHz, or cannot tolerate the 120 ohm
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series resistance, then the Caravan chip provides 11 pads which are
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straight-through connections from core to pad. These pads replace pads
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mprj_io[14] to mprj_io[24] and extend across the top of the padframe.
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WARNING: The analog pads provide NO ESD protection, because the use of
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the pads is open-ended and requirements are different for protection of,
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say, high voltage, negative voltage, and very high frequency.
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All pads other than the 11 that have straight-through connections from
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user project to pad are the same pads as used on Caravel, so there are
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up to 17 GPIO pins that can be used for analog signaling under the same
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restrictions as noted above for Caravel. These pins are given a different
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name on Caravan, which is user_gpio_analog[17:0].
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Because analog circuits will often run at 3.3V, digital circuitry for
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controlling such circuits should use the HVL digital standard cell library
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for 3.3V compatibility. These circuits can connect directly to I/O inputs
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if the io_in_3v3[26:0] pins are used. These pins are copies of the GPIO
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pin digital inputs in the 3.3V domain. Note, however, that there is no
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corresponding GPIO output in the 3.3V domain. 3.3V outputs must be level
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converted into the 1.8V domain using, for example, the cell
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sky130_fd_sc_hvl__lsbufhv2lv_1, before being connected to either io_out
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or io_oeb.
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The full correspondence between mprj_io pins and internal connections is
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shown below, copied from
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caravel_user_project_analog/verilog/rtl/user_analog_proj_example.v:
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Caravan signal connections to I/O pins:
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---------------------------------------------------------------------------------------
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I/O user project user project optional power
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pin digital connection analog connection clamp connection
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---------------------------------------------------------------------------------------
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mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
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mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
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mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
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mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
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mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
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mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
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mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
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mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
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mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
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mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
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mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
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mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
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mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
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mprj_io[24] --- user_analog[10] ---
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mprj_io[23] --- user_analog[9] ---
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mprj_io[22] --- user_analog[8] ---
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mprj_io[21] --- user_analog[7] ---
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mprj_io[20] --- user_analog[6] clamp_high/low[2]
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mprj_io[19] --- user_analog[5] clamp_high/low[1]
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mprj_io[18] --- user_analog[4] clamp_high/low[0]
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mprj_io[17] --- user_analog[3] ---
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mprj_io[16] --- user_analog[2] ---
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mprj_io[15] --- user_analog[1] ---
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mprj_io[14] --- user_analog[0] ---
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mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
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mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
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mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
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mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
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mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
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mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
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mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
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mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
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mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
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mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
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mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
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mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
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mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
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mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
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---------------------------------------------------------------------------------------
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Three of the eleven stright-through analog connections on the Caravel chip
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go to pads which have voltage clamps underneath. A voltage clamp is a
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circuit that protects against ESD events by detecting a rapid rise in
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voltage on a power supply pad, and enabling a switch that shorts the
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power supply to a nearby ground, reducing the event's voltage spike and
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shunting current through a path close to the pads and away from sensitive
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circuitry. Each clamp has a positive connection (clamp_high) and a negative
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connection (clamp_low). Neither of these pins is connected by default. The
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clamp_high pin should be connected to a power supply, preferably the one
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connected to the pad directly above it. The clamp_low pin should be
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connected to a ground return. Due to the nature of the user project wrapper
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as a drop-in module, the current shunting path will be much longer than the
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ideal short path. Be sure to make this path as wide as practicable.
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The clamp circuit is a high-voltage clamp type intended for operation on a
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power supply equal to VDDIO, or nominally 3.3V for the demonstration board
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(and otherwise within the range of 1.8V to 5.5V). Because the I/O voltage
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range includes 1.8V, this clamp will operate at 1.8V. However, it provides
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the best ESD protection for 3.3V supplies. It should not be used with any
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supply higher than VDDIO.
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Because of the large amount of circuitry (the clamp) directly underneath the
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pad, the three pads with the clamps are not intended for high-speed use. These
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pads are best used for additional power supply inputs to the analog chip.
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The three pads that contain clamps are also designed to provide the largest
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amount of current, up to 265mA for each pad (see below). The pin connection
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at the user project wrapper boundary consists of two ports, 25um wide, each
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comprising a stack of metals 3, 4, and 5. To get the maximum current through
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the pad without creating electromigration issues, connect to all three metals
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on both ports.
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Power supply routing on Caravan is expected to be done manually. Allow less
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than 1.5mA per micron width on metal3 and metal4 to satisfy electromigration
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rules, and less than 2.3mA per micron on metal5. The maximum current per
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dedicated power pad is ((25um * 2) * (1.5 + 1.5 + 2.3)) = 265mA.
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Wrapper pins
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--------------------------
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Due to the way the wrapper circuit is "dropped into" the Caravel or Caravan
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harness chip, a continuity check must be run at tape-in to ensure that the
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pins of the wrapper connect correctly to the corresponding locations on the
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harness. This requires that each pin in the design must be on a unique net.
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Because of this requirement, pins in the user wrapper may not be shorted
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together, otherwise only one of the shorted pins can be represented as a
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subcircuit port in the extracted SPICE netlist.
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Because shorting pins together is a likely use case, especially in analog
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designs, the recommended procedure when connecting pins together is to
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place a "metal resistor" in front of the pin connection on all connections
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other than the primary one. Most pin connections are on metal3, so a
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metal3 resistor is preferred. The "metal resistor" in the layout is an
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identifying layer, not a mask layer, so the metal should be continuous
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through to the connection, with the resistor identifier layer spanning the
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width of the connection.
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For example, the user may want to tie together VDDA1 and VDDA2 to double
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the current capacity of the 3.3V domain power supply. The user should
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route a power bus and connect it directly to the VDDA1 pin. Then, a
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route can be made to the VDDA2 pin but should pass through a metal3
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resistor before making the connection to the pin. Any such resistor
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must be represented as a device in a schematic drawing for the design to
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pass LVS.
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Allocating power supplies
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--------------------------
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As mentioned above, power supplies may be connected together if needed.
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These are the available power supplies:
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VCCD1/VSSD1 : User domain 1, 1.8V power
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VCCD2/VSSD2 : User domain 2, 1.8V power
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VDDA1/VSSA1 : User domain 1, 3.3V power
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VDDA2/VSSA2 : User domain 2, 3.3V power
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VDDIO/VSSIO : Management domain, 3.3V power supply to padframe
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VCCD/VSSD : Management domain, 1.8V power supply to padframe and SoC
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All pad connections that are chip pins are in the VDDIO domain. All low
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voltage pad connections to the chip core are in the VCCD domain, and
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the only high voltage pins (io_in_3v3; see above) connected to the user
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project wrapper are in the VDDIO domain.
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Any of the user power supplies that are in the same power domain can be
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connected together to provide additional current capacity. So VCCD1 and
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VCCD2 may be connected together (along with connecting together VSSD1
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and VSSD2); and VDDA1 and VDDA2 may be connected together (along with
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VSSA1 and VSSA2). The user project does not have direct access to the
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management area power domains, including the supplies that drive the
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padframe I/O.
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