mirror of https://github.com/efabless/caravel.git
d4b4b7abb8
knowledge and which went undetected since before MPW-one. Modified the "pll" and "sysctrl" testbenches so that they run and measure something useful. Both exercise the clock monitoring on GPIO outputs functions. The PLL test also runs the digital locked loop (behavioral verilog). The PLL test overlaps sysctrl, but "pll" cannot be run on gate level verilog, whereas "sysctrl" can. |
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| dv | ||
| gl | ||
| rtl | ||
| stubs | ||