mirror of https://github.com/efabless/caravel.git
106 lines
3.0 KiB
ReStructuredText
Executable File
106 lines
3.0 KiB
ReStructuredText
Executable File
.. raw:: html
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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UART interface
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==============
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The UART is a standard 2-pin serial interface that can communicate with the most similar interfaces at a fixed baud rate.
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Although the UART operates independently of the CPU, data transfers are blocking operations which will generate CPU wait states until the data transfer is completed.
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Related pins
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------------
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* :ref:`SER_TX <ser_tx>` - F7,
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* :ref:`SER_RX <ser_rx>` - E7.
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UART control registers
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----------------------
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The behaviour of the UART can be modified by changing values in the registers described below.
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.. _reg_uart_clkdiv:
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``reg_uart_clkdiv``
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~~~~~~~~~~~~~~~~~~~
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Base address: ``0x20000000``
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.. wavedrom::
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{ "reg": [
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{"name": "UART clock divider", "bits": 32}]
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}
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The entire 32bit word encodes the number of CPU core cycles to divide down to get the UART data bit rate (baud rate).
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The default value is 1.
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For example, if the external crystal is 12.5 MHz, then the core CPU clock runs at 100 MHz.
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To get 9600 baud rate, you need to set::
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100 000 000 / 9600 = 10417 (0x28B1)
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.. _reg_uart_data:
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``reg_uart_data``
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~~~~~~~~~~~~~~~~~
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Base address: ``0x20000004``
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.. wavedrom::
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{ "reg": [
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{"name": "UART data", "bits": 8},
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{"name": "(unused, value is 0x0)", "type": 1, "bits": 24}]
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}
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Writing a value to this register will immediately start a data transfer on the :ref:`SER_TX <ser_tx>` pin.
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If the UART write operation is pending, then the CPU will be blocked with wait states until the transfer is complete before starting the new write operation.
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This makes the UART transmit a relatively expensive operation on the CPU, but avoids the necessity of buffering data and checking for buffer overflow.
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Reading a value from this register:
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* returns ``255 (0xff)`` if no valid data byte is in the receive buffer (the whole register has value ``0xffffffff``), or
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* returns the value of the received buffer otherwise, and
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* clears the receive buffer for additional reads.
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.. note:: There is no FIFO associated with the UART.
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.. _reg_uart_enable:
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``reg_uart_enable``
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~~~~~~~~~~~~~~~~~~~
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Base address: ``0x20000008``
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.. wavedrom::
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{ "reg": [
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{"name": "UART enable", "bits": 8},
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{"name": "(unused, value is 0x0)", "type": 1, "bits": 24}]
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}
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The UART must be enabled to run (disabled by default).
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