mirror of https://github.com/efabless/caravel.git
389 lines
10 KiB
ReStructuredText
Executable File
389 lines
10 KiB
ReStructuredText
Executable File
.. raw:: html
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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General Purpose Input/Output
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============================
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The GPIO pin is a single assignable general-purpose digital input or output that is available only to the management SoC and cannot be assigned to the user project area.
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On the test board provided with the completed user projects, this pin is used to enable the voltage regulators generating the user area power supplies.
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The basic function of the GPIO is illustrated in :ref:`gpio_structure`.
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All writes to :ref:`reg_gpio_data` are registered.
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All reads from :ref:`reg_gpio_data` are immediate.
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.. figure:: _static/gpio.svg
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:name: gpio_structure
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:alt: GPIO channel structure
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:align: center
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GPIO channel structure
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Register descriptions
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~~~~~~~~~~~~~~~~~~~~~
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.. list-table:: GPIO memory address map
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:name: gpio_memory_address_map
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:header-rows: 1
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* - C header name
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- Address
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- Description
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* - :ref:`reg_gpio_data`
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- ``0x21000000``
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- GPIO input/output (low bit)
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GPIO output readback (16th bit)
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* - :ref:`reg_gpio_ena`
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- ``0x21000004``
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- GPIO output enable (`0 = output`, `1 = input`)
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* - :ref:`reg_gpio_pu`
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- ``0x21000008``
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- GPIO pullup enable (`0 = none`, `1 = pullup`)
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* - :ref:`reg_gpio_pd`
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- ``0x2100000c``
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- GPIO pulldown enable (`0 = none`, `1 = pulldown`)
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* - :ref:`reg_pll_out_dest`
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- ``0x2f000000``
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- PLL clock output destination (low bit)
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* - :ref:`reg_trap_out_dest`
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- ``0x2f000004``
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- Trap output destination (low bit)
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* - :ref:`reg_irq7_source`
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- ``0x2f000008``
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- IRQ 7 input source (low bit)
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.. note::
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In the registers description below, each register is shown as 32 bits corresponding
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to the data bus width of the wishbone bus. Depending on the instruction and data type,
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the entire 32-bit register can be read in one instruction, or one 16-bit word,
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or one 8-bit byte.
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.. _reg_gpio_data:
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``reg_gpio_data``
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-----------------
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Base address: ``0x21000000``
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.. wavedrom::
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{ "reg": [
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{"name": "GPIO input/output", "bits": 16},
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{"name": "GPIO output readback", "bits": 16}]
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}
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* Writing to the address low bit always sets the registered value at the GPIO.
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* Writing to address bit 16 has no effect.
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* Reading from the address low bit reads the value at the chip pin.
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* Reading from address bit 16 reads the value at the multiplexer output (see :ref:`gpio_structure`).
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.. _reg_gpio_ena:
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``reg_gpio_ena``
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----------------
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Base address: ``0x21000004``
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.. wavedrom::
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{ "reg": [
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{"name": "GPIO output enable", "bits": 16},
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{"name": "(undefined, reads zero)", "bits": 16, "type": 1}]
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}
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* Bit 0 corresponds to the GPIO channel enable.
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* Bit value 1 indicates an output channel; 0 indicates an input.
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.. _reg_gpio_pu:
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``reg_gpio_pu``
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---------------
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Base address: ``0x21000008``
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.. wavedrom::
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{ "reg": [
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{"name": "GPIO pin pull-up", "bits": 16},
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{"name": "(undefined, reads zero)", "bits": 16, "type": 1}]
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}
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* Bit 0 corresponds to the GPIO channel pull-up state.
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* Bit value 1 indicates pullup is active; 0 indicates pullup is inactive.
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.. _reg_gpio_pd:
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``reg_gpio_pd``
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---------------
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Base address: ``0x2100000c``
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.. wavedrom::
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{ "reg": [
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{"name": "GPIO pin pull-down (inverted)", "bits": 16},
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{"name": "(undefined, reads zero)", "bits": 16, "type": 1}]
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}
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.. todo:: The statement below (second sentence) seems to be invalid.
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* Bit 0 corresponds to the GPIO channel pull-down state.
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* Bit value 1 indicates pullup is active; 0 indicates pulldown is inactive.
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.. _reg_pll_out_dest:
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``reg_pll_out_dest``
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--------------------
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Base address: ``0x2f000000``
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.. wavedrom::
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{ "reg": [
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{"name": "PLL clock dest.", "bits": 8},
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{"name": "(undefined, reads zero)", "bits": 24, "type": 1}]
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}
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The PLL clock (crystal oscillator clock multiplied up by PLL) can be viewed on the GPIO pin.
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The GPIO pin cannot be used as general-purpose I/O when selected for PLL clock output.
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The low bit of this register directs the output of the core clock to the GPIO channel, according to the :ref:`reg_pll_out_dest_table`.
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.. list-table:: ``reg_pll_out_dest`` register settings
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:name: reg_pll_out_dest_table
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:header-rows: 1
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* - ``0x2f000000`` value
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- Clock output directed to this channel
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* - ``0``
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- (none)
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* - ``1``
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- Core PLL clock to GPIO output
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.. note::
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High rate core clock (e.g. 80MHz) may be unable to generate a full swing on the GPIO output, but is detectable.
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.. _reg_trap_out_dest:
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``reg_trap_out_dest``
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---------------------
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Base address: ``0x2f000004``
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.. wavedrom::
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{ "reg": [
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{"name": "trap signal dest.", "bits": 8},
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{"name": "(undefined, reads zero)", "bits": 24, "type": 1}]
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}
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The CPU fault state (trap) can be viewed at the GPIO pin as a way to monitor the CPU trap state externally.
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The low bit of this register directs the output of the processor trap signal to the GPIO channel, according to the :ref:`reg_trap_out_dest_table`.
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.. list-table:: ``reg_trap_out_dest`` register settings
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:name: reg_trap_out_dest_table
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:header-rows: 1
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* - ``0x2f000004`` value
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- Trap signal output directed to this channel
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* - ``0``
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- (none)
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* - ``1``
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- GPIO
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.. _reg_irq7_source:
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``reg_irq7_source``
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-------------------
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Base address: ``0x2f000008``
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.. wavedrom::
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{ "reg": [
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{"name": "IRQ 7 source", "bits": 8},
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{"name": "(undefined, reads zero)", "bits": 24, "type": 1}]
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}
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The GPIO input can be used as an IRQ event source and passed to the CPU through IRQ channel 7 (see :doc:`irq`).
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When used as an IRQ source, the GPIO pin must be configured as an input.
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The low bit of this register directs the input of the GPIO to the processor's IRQ7 channel, according to the :ref:`reg_irq7_source_table`.
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.. list-table:: ``reg_irq7_source`` register settings
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:name: reg_irq7_source_table
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:header-rows: 1
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* - Register byte
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- ``0x2f000008`` value
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- This channel directed to IRQ channel 7
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* - 0
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- ``00``
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- (none)
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* - 1
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- ``01``
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- GPIO
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User project area GPIO
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~~~~~~~~~~~~~~~~~~~~~~
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.. todo::
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This section is based on Memory mapped I/O summary by address from PDF documentation.
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It needs some elaboration.
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.. _reg_mprj_io_configure:
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User project area GPIO ``mprj_io[37:0]`` configure registers
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------------------------------------------------------------
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Each of 38 ``mprj_io`` GPIOs has a configuration register.
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.. csv-table:: Base addresses for ``mprj_io`` configuration registers
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:name: reg_mprj_io_configure_addresses
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:widths: auto
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:header-rows: 1
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:delim: ;
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User project area GPIO ; Address
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``mprj_io[00]`` ; ``0x2600000c``
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``mprj_io[01]`` ; ``0x26000010``
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``mprj_io[02]`` ; ``0x26000014``
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``mprj_io[03]`` ; ``0x26000018``
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``mprj_io[04]`` ; ``0x2600001c``
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``mprj_io[05]`` ; ``0x26000020``
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``mprj_io[06]`` ; ``0x26000024``
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``mprj_io[07]`` ; ``0x26000028``
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``mprj_io[08]`` ; ``0x2600002c``
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``mprj_io[09]`` ; ``0x26000030``
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``mprj_io[10]`` ; ``0x26000034``
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``mprj_io[11]`` ; ``0x26000038``
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``mprj_io[12]`` ; ``0x2600003c``
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``mprj_io[13]`` ; ``0x26000040``
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``mprj_io[14]`` ; ``0x26000044``
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``mprj_io[15]`` ; ``0x26000048``
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``mprj_io[16]`` ; ``0x2600004c``
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``mprj_io[17]`` ; ``0x26000050``
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``mprj_io[18]`` ; ``0x26000054``
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``mprj_io[19]`` ; ``0x26000058``
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``mprj_io[20]`` ; ``0x2600005c``
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``mprj_io[21]`` ; ``0x26000060``
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``mprj_io[22]`` ; ``0x26000064``
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``mprj_io[23]`` ; ``0x26000068``
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``mprj_io[24]`` ; ``0x2600006c``
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``mprj_io[25]`` ; ``0x26000070``
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``mprj_io[26]`` ; ``0x26000074``
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``mprj_io[27]`` ; ``0x26000078``
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``mprj_io[28]`` ; ``0x2600007c``
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``mprj_io[29]`` ; ``0x26000080``
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``mprj_io[30]`` ; ``0x26000084``
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``mprj_io[31]`` ; ``0x26000088``
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``mprj_io[32]`` ; ``0x2600008c``
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``mprj_io[33]`` ; ``0x26000090``
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``mprj_io[34]`` ; ``0x26000094``
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``mprj_io[35]`` ; ``0x26000098``
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``mprj_io[36]`` ; ``0x2600009c``
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``mprj_io[37]`` ; ``0x260000a0``
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.. wavedrom::
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{ "reg": [
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"bits": 1, "type": 2},
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{"name": "mode", "bits": 3, "type": 1},
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{"bits": 19, "type": 1}]
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}
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.. todo:: Missing default values
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.. todo:: Missing setting descriptions
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.. list-table:: ``mprj_io[i]`` control register descriptions
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:name: reg_mprj_io_configure_description
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:header-rows: 1
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:widths: auto
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* - Mask bit
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- Default
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- Description
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* - 10-12
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- ``001``
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- Digital mode
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* - 9
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- TODO
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- input voltage trip point select
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* - 8
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- 0
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- slow slew (0 - fast slew, 1 - slow slew)
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* - 7
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- TODO
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- analog bus polarity
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* - 6
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- TODO
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- analog bus select
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* - 5
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- TODO
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- analog bus enable (0 - disabled, 1 - enabled)
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* - 4
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- TODO
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- IB mode select
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* - 3
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- 0
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- input disable (0 - input enabled, 1 - input disabled)
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* - 2
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- 0
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- hold override value (value is the value during hold mode)
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* - 1
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- 1
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- output disable (0 - output enabled, 1 - output disabled)
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* - 0
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- 1
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- management control enable (0 - user control, 1 - management control)
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.. todo:: Missing *digital mode* description
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