Tim Edwards be98da0fe6 Added spare logic block to caravel layout and verilog GL, wired ... it to the power supply, and checked top-level LVS.		2021-11-24 16:50:22 -05:00
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dv	Update storage testbench to work with one 2K block	2021-11-12 17:14:21 +02:00
gl	Added spare logic block to caravel layout and verilog GL, wired	2021-11-24 16:50:22 -05:00
rtl	Revised the spare logic block to make sure that all inputs are	2021-11-24 09:34:52 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00