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riscv
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caravel
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https://github.com/efabless/caravel.git
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bd88221d17
caravel
/
verilog
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manarabdelaty
bd88221d17
[DATA] Update caravel_clocking
2021-12-07 13:36:56 +02:00
..
dv
Fixed one bad error in clock_div which had been done without my
2021-12-06 21:37:51 -05:00
gl
[DATA] Update caravel_clocking
2021-12-07 13:36:56 +02:00
rtl
Fixed one bad error in clock_div which had been done without my
2021-12-06 21:37:51 -05:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00