mirror of https://github.com/efabless/caravel.git
024801ab56
verilog gate-level netlists to match the correct GPIO default value assignments, and modify the top level gate-level caravel.v and caravan.v netlists to match. |
||
---|---|---|
.. | ||
check_density.py | ||
compositor.py | ||
count_lvs.py | ||
create-caravel-diagram.py | ||
gen_gpio_defaults.py | ||
generate_fill.py | ||
generate_fill_orig.py | ||
make_bump_bonds.tcl | ||
set_user_id.py |