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riscv
/
caravel
mirror of
https://github.com/efabless/caravel.git
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bb2d983e03
caravel
/
verilog
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kareem
bb2d983e03
+ add a size 16 buf for clockp signal in digital_pll
2022-10-13 05:57:09 -07:00
..
dv
added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list
2022-10-10 06:23:47 -07:00
gl
~ regenerate chip_io netlist to fix missing power pins from constant blocks
2022-10-12 11:40:05 -07:00
rtl
+ add a size 16 buf for clockp signal in digital_pll
2022-10-13 05:57:09 -07:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00