mirror of https://github.com/efabless/caravel.git
34 lines
1018 B
Verilog
34 lines
1018 B
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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module mprj2_logic_high (
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`ifdef USE_POWER_PINS
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inout vccd2,
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inout vssd2,
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`endif
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output HI
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);
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sky130_fd_sc_hd__conb_1 inst (
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`ifdef USE_POWER_PINS
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.VPWR(vccd2),
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.VGND(vssd2),
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.VPB(vccd2),
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.VNB(vssd2),
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`endif
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.HI(HI),
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.LO()
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);
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endmodule
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