caravel/verilog
Tim Edwards bb1c9fe528 Removed two references for single-macro verilog files that are no
longer in the PDK but have been folded into larger library files.
With the most recent push to open_pdks to fix an error in the I/O
verilog library, the verilog testbenches once again pass.
2021-11-15 17:53:48 -05:00
..
dv Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
gl [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
rtl Removed two references for single-macro verilog files that are no 2021-11-15 17:53:48 -05:00