mirror of https://github.com/efabless/caravel.git
91 lines
2.5 KiB
Tcl
91 lines
2.5 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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# User config
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set verilog_root $::env(CARAVEL_ROOT)/verilog/
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set lef_root $::env(CARAVEL_ROOT)/lef/
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set gds_root $::env(CARAVEL_ROOT)/gds/
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set ::env(DESIGN_NAME) caravan
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set ::env(ROUTING_CORES) 2
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# Change if needed
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set ::env(VERILOG_FILES) "\
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$verilog_root/rtl/user_defines.v \
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$verilog_root/rtl/defines.v \
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$verilog_root/rtl/caravan.v"
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set ::env(SYNTH_READ_BLACKBOX_LIB) 0
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$verilog_root/rtl/caravan_logo.v \
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$verilog_root/rtl/caravan_motto.v \
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$verilog_root/rtl/copyright_block_a.v \
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$verilog_root/rtl/open_source.v \
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$verilog_root/rtl/user_id_textblock.v \
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$verilog_root/rtl/defines.v \
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$verilog_root/rtl/pads.v \
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$verilog_root/rtl/chip_io_alt.v \
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$verilog_root/gl/caravan_core.v"
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set ::env(EXTRA_LEFS) "\
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$lef_root/caravan_logo-stub.lef \
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$lef_root/caravan_motto-stub.lef \
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$lef_root/copyright_block_a-stub.lef \
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$lef_root/open_source-stub.lef \
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$lef_root/user_id_textblock-stub.lef \
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$lef_root/chip_io_alt.lef \
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$lef_root/caravan_core.lef"
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set ::env(EXTRA_GDS_FILES) "\
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$gds_root/copyright_block_a.gds \
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$gds_root/open_source.gds \
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$gds_root/user_id_textblock.gds \
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$gds_root/caravan_logo.gds \
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$gds_root/caravan_motto.gds \
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$gds_root/chip_io_alt.gds \
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$gds_root/caravan_core.gds"
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set ::env(SYNTH_ELABORATE_ONLY) 1
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set ::env(LEC_ENABLE) 0
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set ::env(FP_SIZING) absolute
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set fd [open "$::env(DESIGN_DIR)/../chip_dimensions.txt" "r"]
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set ::env(DIE_AREA) [read $fd]
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close $fd
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set ::env(CELL_PAD) 0
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(DIODE_INSERTION_STRATEGY) 0
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set ::env(GRT_ALLOW_CONGESTION) 1
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set ::env(RUN_FILL_INSERTION) 0
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# DON'T PUT CELLS ON THE TOP LEVEL
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set ::env(LVS_INSERT_POWER_PINS) 0
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set ::env(MAGIC_GENERATE_LEF) 0
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set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
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set ::env(QUIT_ON_TR_DRC) 0
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set ::env(QUIT_ON_LVS_ERROR) 1
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set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
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