caravel/verilog
marwaneltoukhy b07d91ef7a resolve conflict 2022-10-13 12:11:42 -07:00
..
dv resolve conflict 2022-10-13 12:11:42 -07:00
gl ~ regenerate chip_io netlist to fix missing power pins from constant blocks 2022-10-12 11:40:05 -07:00
rtl fix bug of wrapper ack 2022-10-11 06:02:44 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00