caravel/verilog
R. Timothy Edwards ad8d168555
Corrects four signal routes which were missing from the caravan top level (#88)
* Corrects four signals which were missing from the caravan top level
(management output and output enable to GPIO 0 and 1---these errors
would have prevented the houskeeping SPI from working on caravel).
Corrected RTL verilog (source of the error), GL verilog, and layout.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-25 08:50:55 -07:00
..
dv Introduction of PDK variable (#39) 2022-04-08 09:05:58 -07:00
gl Corrects four signal routes which were missing from the caravan top level (#88) 2022-04-25 08:50:55 -07:00
rtl Corrects four signal routes which were missing from the caravan top level (#88) 2022-04-25 08:50:55 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00