mirror of https://github.com/efabless/caravel.git
29 lines
861 B
Verilog
29 lines
861 B
Verilog
module constant_block (one,
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zero);
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output one;
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output zero;
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wire one_unbuf;
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wire zero_unbuf;
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sky130_fd_sc_hd__buf_16 const_one_buf (.A(one_unbuf),
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.X(one));
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sky130_fd_sc_hd__conb_1 const_source (.HI(one_unbuf),
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.LO(zero_unbuf));
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sky130_fd_sc_hd__buf_16 const_zero_buf (.A(zero_unbuf),
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.X(zero));
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sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_0 ();
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sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1 ();
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sky130_fd_sc_hd__fill_2 FILLER_0_0 ();
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sky130_fd_sc_hd__fill_2 FILLER_0_24 ();
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sky130_fd_sc_hd__fill_1 FILLER_0_27 ();
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sky130_fd_sc_hd__fill_4 FILLER_1_0 ();
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sky130_fd_sc_hd__fill_1 FILLER_1_4 ();
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sky130_fd_sc_hd__fill_8 FILLER_1_8 ();
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sky130_fd_sc_hd__fill_8 FILLER_1_16 ();
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sky130_fd_sc_hd__fill_4 FILLER_1_24 ();
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sky130_fd_sc_hd__fill_2 FILLER_2_0 ();
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sky130_fd_sc_hd__fill_2 FILLER_2_24 ();
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sky130_fd_sc_hd__fill_1 FILLER_2_27 ();
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endmodule
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