Tim Edwards e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master ... since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.		2021-10-21 19:48:24 -04:00
..
__uprj_analog_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__uprj_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__user_analog_project_wrapper.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__user_project_wrapper.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravan.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravan_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravel.v	Corrected the last testbenches, added a new testbench for the spi_master	2021-10-21 19:48:24 -04:00
caravel_clocking.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravel_netlists.v	First major update; current code passes syntax checks in iverilog	2021-10-15 21:49:49 -04:00
caravel_openframe.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
chip_io.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
chip_io_alt.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
clock_div.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
defines.v	Correction to the mprj_bitbang testbench to run the test without running	2021-10-21 10:57:20 -04:00
digital_pll.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
digital_pll_controller.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
gpio_control_block.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
gpio_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
housekeeping.v	Corrected the last testbenches, added a new testbench for the spi_master	2021-10-21 19:48:24 -04:00
housekeeping_spi.v	First major update; current code passes syntax checks in iverilog	2021-10-15 21:49:49 -04:00
mgmt_protect.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mgmt_protect_hv.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj2_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj_io.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
pads.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
ring_osc2x13.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
simple_por.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
user_id_programming.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00