mirror of https://github.com/efabless/caravel.git
371 lines
18 KiB
Python
371 lines
18 KiB
Python
from audioop import add
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from ctypes import BigEndianStructure
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from operator import truediv
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from cocotb import top
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import cocotb
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from cocotb.binary import BinaryValue
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from cocotb.triggers import Timer, RisingEdge, ReadOnly
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import fnmatch
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import copy
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import logging
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from cocotb.result import TestFailure
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from cocotb_coverage.coverage import *
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class HK_models():
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def __init__(self,reg_model,expeceted_output,hk_hdl):
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self.reg_model = reg_model
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self.expeceted_output = expeceted_output
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self.hk_hdl = hk_hdl
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self.old_hold_val = 1
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self.gpio_out_pre = BinaryValue(value=0,n_bits=38,bigEndian=False)
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self.mgmt_gpio_oeb = BinaryValue(value=0,n_bits=38,bigEndian=False)
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self.exp_out_wb = [] # expected output for wishbone
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self.exp_out_uart_rx = [self.expeceted_output['UART']] # expected output for uart
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self.exp_out_debug = [self.expeceted_output['debug']] # expected output for
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self.exp_out_spi = [self.expeceted_output['SPI']] # expected output for
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self.reset_spi_vals(True)
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self.input_dis =3
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self.regs_full_list()
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self.intial_cov()
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"""model for the wishbone interface with housekeeping"""
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def wishbone_model(self,trans):
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clock_signal = trans["_clk"]["signal"]
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if trans["stb"]["val"] == 1 : # valid data
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address = trans["adr"]["val"]
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data = trans["data"]["val"]
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# if ack isn't realsead don't care about the new input it must be the same as the old and the monitor checks that
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if (self.old_hold_val == 0):
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self.old_hold_val = trans["_hold"]["val"]
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return
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self.old_hold_val = trans["_hold"]["val"]
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if trans["write_en"]["val"] ==1 : # write cycle
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cocotb.log.debug(f'[HK_models][_valid_address] write enable for address: {hex(address)} and data: {hex(data)} ')
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select = trans["sel"]["val"]
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cocotb.scheduler.add(self._write_reg_wb(address,data,select,clock_signal))
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else: #read cycle
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self.write_exp_out_wb(self._read_reg_wb(address))
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self.wishbone_last_trans = trans
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"""model for the system interface with housekeeping"""
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def system_model(self,trans):
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self.reg_model['sys']['0x00'][0][6] = trans["vdd2_good"]["val"]
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self.reg_model['sys']['0x00'][1][6] = trans["vdd1_good"]["val"]
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self.reg_model['sys']['0x00'][2][6] = trans["vcc2_good"]["val"]
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self.reg_model['sys']['0x00'][3][6] = trans["vcc1_good"]["val"]
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"""model for the UART interface with housekeeping"""
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def UART_model(self,trans):
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# when transmiting TX the gpio data out should change to the tx value
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if trans["enable"]["val"]:
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self.gpio_out_pre[6]= trans["TX"]["val"].value
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else:
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gpio_data = self._read_reg_keys(["GPIO","0x0c"]) # mgmt_gpio_data[7:0]
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self.gpio_out_pre[6]= int(gpio_data[len(gpio_data)-1 -6]) # mgmt_gpio_data[6]
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# predecting the rx output value when the value UART is enble is the value drom pin [5]
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gpio_in_size = trans["gpio_in"]["val"].n_bits -1
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output = self.expeceted_output['UART']
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output["RX"]["val"] = 0
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if trans["enable"]["val"]:
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output["RX"]["val"] = trans["gpio_in"]["val"][gpio_in_size-5] #gpio_in[5]
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self.exp_out_uart_rx.append(output)
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"""model for the debug interface with housekeeping"""
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def debug_model(self,trans):
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# when debug is enable gpio out [0] should follow debug_out
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if trans["enable"]["val"]:
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self.gpio_out_pre[0] = trans["data"]["val"].value
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self.mgmt_gpio_oeb[0] = trans["data"]["val"].value
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else:
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gpio_data = self._read_reg_keys(["GPIO","0x0c"]) # mgmt_gpio_data[7:0]
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self.gpio_out_pre[0]= int(gpio_data[len(gpio_data)-1 -0]) # mgmt_gpio_data[6]
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gpio_data_en = self._read_reg_keys(["GPIO","0x24"]) # gpio_configure[0][7:0]
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self.mgmt_gpio_oeb[0]= 1- int(gpio_data[len(gpio_data_en)-1 -self.input_dis]) # gpio_configure[0][3]
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# predecting the debug in signal when debug mode is enbled taking the value from pin [0]
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gpio_in_size = trans["gpio_in"]["val"].n_bits -1
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output = self.expeceted_output['debug']
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output["data"]["val"] = 0
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if trans["enable"]["val"]:
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output["data"]["val"] = trans["gpio_in"]["val"][gpio_in_size-0] # mgmt_gpio_in[0]
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self.exp_out_debug.append(output)
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"""model for the SPI interface with housekeeping"""
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def spi_model(self,trans):
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output = self.expeceted_output['SPI']
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output["SDO"]["val"] = 0
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cocotb.log.debug(f'[HK_models][spi_model] spi mode {self.spi_mode[0]} bit number {self.spi_mode[1]} command = {self.command_spi} address = {self.address_spi} write = {self.write_spi} stream = {self.spi_mode[2]}')
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if self.spi_mode[0] == "command":
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self._setCommand(trans['SDI']['val'].binstr)
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self.exp_out_spi.append(output)
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elif self.spi_mode[0] == "address":
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self._setAddress(trans['SDI']['val'].binstr)
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self.exp_out_spi.append(output)
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elif self.spi_mode[0] == "write":
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self._setWriteData(trans['SDI']['val'].binstr)
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self.exp_out_spi.append(output)
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elif self.spi_mode[0] == "read":
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output["SDO"]["val"] = self._getReadData()
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self.exp_out_spi.append(output)
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elif self.spi_mode[0] == "read/write":
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output["SDO"]["val"] = self._getReadData()
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self.exp_out_spi.append(output)
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elif self.spi_mode[0] == "noOP":
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self._setWriteData(trans['SDI']['val'].binstr)
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else:
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raise TestFailure("[HK_models][spi_model] invalid command type")
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"""reset the spi vals when CSB is going from low to high"""
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def reset_spi_vals(self,trans):
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cocotb.log.info(f"[HK_models][reset_spi_vals] CSB is disabled")
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self.spi_mode = ["command",0,0] # [mode type, bit number, stream number]
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self.command_spi = ['0']*8
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self.address_spi = ['0']*8
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self.write_spi = ['0']*8
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self.read_spi = ['0']*8
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def _setCommand(self,bit):
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if bit not in ['0','1']:
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cocotb.log.warning(f"[HK_models][_setCommand] incorrect bit size bit = {bit}")
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self.command_spi[self.spi_mode[1]] = bit
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self.spi_mode[1] += 1
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self.spi_mode[2] = 0 # stream number
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if self.spi_mode[1] >= 8:
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self.spi_mode[0] = "address"
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self.spi_mode[1] = 0
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def _setAddress(self,bit):
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if bit not in ['0','1']:
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cocotb.log.warning(f"[HK_models][_setAddress] incorrect bit size bit = {bit}")
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self.address_spi[self.spi_mode[1]] = bit
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self.spi_mode[1] += 1
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self.spi_mode[2] = 0 # stream number
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if self.spi_mode[1] >= 8:
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self.spi_mode[1] = 0
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if self.command_spi[0:2] == ['0','0']:
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self.spi_mode[0] = "noOP"
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if self.command_spi[0:2] == ['1','0']:
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self.spi_mode[0] = "write"
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if self.command_spi[0:2] == ['0','1']:
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self.spi_mode[0] = "read"
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if self.command_spi[0:2] == ['1','1']:
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self.spi_mode[0] = "read/write"
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def _setWriteData(self,bit):
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if bit not in ['0','1']:
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cocotb.log.warning(f"[HK_models][_setWriteData] incorrect bit size bit = {bit}")
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# return if write is write n-bytes command and number of bytes exceeds the required
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if self.command_spi[2:5] != ['0','0','0']:
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self.spi_mode_cov('write-n')
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byte_num = int(''.join(self.command_spi[2:5]),2)
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if byte_num <= self.spi_mode[2]: #number of written byte <= stream number
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self.spi_mode[0] = "noOP"
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return
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else: self.spi_mode_cov('write')
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self.write_spi[self.spi_mode[1]] = bit
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self.spi_mode[1] += 1
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if self.spi_mode[1] >= 8:
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self.spi_mode[1] = 0
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address = int(''.join(self.address_spi),2) + self.spi_mode[2]
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data = ''.join(self.write_spi)
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data = BinaryValue(value = data, n_bits =8)
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is_valid, keys=self._valid_address_spi(address)
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if is_valid:
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self.reg_cov(keys[0],keys[1],is_read=False)
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cocotb.log.debug(f'[HK_models][_valid_address] writing {data} to memory:{keys[0]} field: {keys[1]} through housekeeping SPI address = {address}')
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self._write_fields(keys,data)
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if self.command_spi[2:5] != ['0','0','0']:self.spi_mode_cov('write-n')
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else: self.spi_mode_cov('write')
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self.spi_mode[2] += 1 # stream number
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def _getReadData(self):
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# return if write is write n-bytes command and number of bytes exceeds the required
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if self.command_spi[2:5] != ['0','0','0']:
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byte_num = int(''.join(self.command_spi[2:5]),2)
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if byte_num <= self.spi_mode[2]: #number of written byte <= stream number
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self.spi_mode[0] = "noOP"
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return
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bit_num = self.spi_mode[1]
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address = int(''.join(self.address_spi),2) + self.spi_mode[2]
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is_valid, keys=self._valid_address_spi(address)
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data = ''
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if is_valid:
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self.reg_cov(keys[0],keys[1])
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cocotb.log.info(f'[HK_models][_getReadData] reading from memory:{keys[0]} field: {keys[1]} through SPI')
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for field in self.reg_model[keys[0]][keys[1]]:
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data = str(bin(field[6])[2:]).zfill(field[3]) + data
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data = data.zfill(8)
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cocotb.log.info(f'[HK_models][_getReadData] reading from memory:{keys[0]} field: {keys[1]} through SPI data {data} bit[{7-bit_num}] = {data[bit_num]}')
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self.spi_mode[1] += 1
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if self.spi_mode[1] >= 8:
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self.spi_mode[1] = 0
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self.spi_mode[2] += 1 # stream number
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if self.command_spi[2:5] != ['0','0','0']:self.spi_mode_cov('read-n')
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else: self.spi_mode_cov('read')
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if data == '':
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return 0
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return int(data[bit_num],2)
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def write_exp_out_wb(self,data):
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output = self.expeceted_output['wishbone']
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output['ack']['val'] = 1
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output['_valid_cycle']['val'] = 1
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output['data']['val'] = BinaryValue(value = data,n_bits = 32,bigEndian=False)
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self.exp_out_wb.append(output)
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"""write register through wishbone """
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async def _write_reg_wb(self,address,data,select,clk):
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old_data = self._read_reg_wb(address)
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self.write_exp_out_wb(old_data)
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if address == 0x2600000c: # mgmt_gpio_data is a special case as it got written completely at the end of the serial writing
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for i in range(6):
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await RisingEdge(self.hk_hdl._id(clk,False))
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for i in range(3):
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await RisingEdge(self.hk_hdl._id(clk,False))
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for i,sel in enumerate(select.binstr):
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temp_addr = BinaryValue(value=(address.value +i))
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if sel is '1':
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is_valid, keys=self._valid_address(temp_addr)
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if is_valid:
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self.reg_cov(keys[0],keys[1],is_SPI=False,is_read=False)
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cocotb.log.debug(f'[HK_models][_valid_address] writing {data[(8*((4-i-1))):8*(4-i)-1]} to memory:{keys[0]} field: {keys[1]}')
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temp_data = data[(8*((4-i-1))):8*(4-i)-1]
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self._write_fields(keys,temp_data)
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cocotb.log.debug(f" [HK_models][_valid_address] address {hex(address)} used for access housekeeping memory success")
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if address != 0x2600000c:
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for i in range(2):
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await RisingEdge(self.hk_hdl._id(clk,False))
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def _write_fields(self,keys,data):
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for field in self.reg_model[keys[0]][keys[1]]:
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if field[4] == "RW":
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shift = field[2]
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size = field[3]
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cocotb.log.debug(f'[HK_models][_write_fields] before update field : {field[1]} data = {bin(field[6])} with data {data[shift:shift+size-1]} ')
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field[6] = data[8-shift-size:8-shift-1]
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cocotb.log.debug(f'[HK_models][_write_fields] after update field : {field[1]} data = {bin(field[6])} with data {data[shift:shift+size-1]} ')
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"""read register value using keys return size binary value"""
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def _read_reg_keys(self,keys:list):
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size =0
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data = ""
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for field in self.reg_model[keys[0]][keys[1]]:
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size += field[3]
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data += bin(field[6])[2:].zfill(size)
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return data
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"""read register through wishbone """
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def _read_reg_wb(self,address):
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total_size = 32
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data_string ="0"
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data_out = list(bin(0)[2:].zfill(total_size))
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for i in range(4):
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temp_addr = BinaryValue(value=(address.value +i))
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is_valid, keys=self._valid_address(temp_addr)
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if is_valid:
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self.reg_cov(keys[0],keys[1],is_SPI=False)
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for field in self.reg_model[keys[0]][keys[1]]:
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shift = field[2]
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size = field[3]
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first_index = ((8 *(4-i))) - shift-size
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second_index = ((8 *(4-i))) - shift
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data = bin(field[6])[2:].zfill(size)
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cocotb.log.debug(f"[HK_models][_read_reg] memory:{keys[0]} shift:{keys[1]} field:{field[0]} data:{data} ")
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for k,j in enumerate(range(first_index, second_index, 1)):
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data_out[j] = data[k]
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data_string = "".join(data_out)
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cocotb.log.debug(f"[HK_models][_read_reg] register {hex(address)} has value {hex(int(data_string,2))} ")
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return int(data_string,2)
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"""return false if the address isn't exist inside housekeeping if the address exist return true and the key of address in JSON file"""
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def _valid_address(self,address):
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size = max(len(address),32)
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address = address.binstr.zfill(size)
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for key,memory in self.reg_model.items():
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if fnmatch.fnmatch(key, "_*") :
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continue
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# remove the first 2 element 0b and
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base_addr= bin(memory["base_addr"][1])[2:].zfill(size)
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cocotb.log.debug(f'[HK_models][_valid_address] base address[:13]={hex(int(base_addr[size-32:size-13],2))} target address[:13]={hex(int(address[size-32:size-13],2))} shift={"{0:#0{1}x}".format(int(address[size-12:],2),4)}')
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if base_addr[size-32:size-13] == address[size-32:size-13]:
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if "{0:#0{1}x}".format(int(address[size-12:],2),4) in memory:
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cocotb.log.debug(f'[HK_models][_valid_address] base address={hex(int(base_addr,2))} key {key}')
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return True, [key,"{0:#0{1}x}".format(int(address[size-12:],2),4)]
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cocotb.log.warning(f"[HK_models][_valid_address] address {hex(int(address,2))} used for access housekeeping memory isn't valid")
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return False, None
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"""return false if the address isn't exist inside housekeeping if the address exist return true and the key of address in JSON file"""
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def _valid_address_spi(self,address):
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for key,memory in self.reg_model.items():
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if fnmatch.fnmatch(key, "_*") :
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continue
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for key2,reg in memory.items():
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if key2 == "base_addr" :
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continue
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for field in reg:
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if field[7] == address:
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return True,[key,key2]
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cocotb.log.warning(f"[HK_models][_valid_address_spi] address {hex(address)} for SPI housekeeping isn't valid")
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return False, None
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######################## coverage ############################
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def regs_full_list(self):
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bins = list()
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labels = list()
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for key,mem in self.reg_model.items():
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if fnmatch.fnmatch(key, "_*"):
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continue
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for key2,fields in mem.items():
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if key2=='base_addr':
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continue
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bins.append((key,key2))
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labels.append((self.reg_model[key][key2][0][0]))
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self.reg_bins = bins
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self.reg_labels = labels
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def intial_cov(self):
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for i in [True,False]:
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for j in [True,False]:
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self.reg_cov(0,0,i,j)
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self.spi_mode_cov(0)
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def reg_cov(self,key1,key2,is_SPI=True,is_read=True):
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s=''
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if is_SPI:
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s = "spi."
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else:
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s="wishbone."
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if is_read:
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s +="read"
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else:
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s+= "write"
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@CoverPoint(f"top.caravel.housekeeping.regs.{s}",
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xf = lambda key1,key2:(key1,key2),
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bins = self.reg_bins,
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bins_labels=self.reg_labels)
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def cov(key1,key2):
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pass
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cov(key1,key2)
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return (key1,key2)
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def spi_mode_cov(self,mode):
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@CoverPoint(f"top.caravel.housekeeping.spi.modes",
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bins = ['noOP','write','read','read/write','write-n','read-n','read/write-n','Pass-m','pass-u'],
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bins_labels=['No operation','Write in streaming mode','Read in streaming mode','Simultaneous Read/Write in streaming mode','Write in n-byte mode','Read in n-byte mode','Simultaneous Read/Write in n-byte mode','Pass-through (management) Read/Write streaming mode','Pass-through (user) Read/Write in streaming mode' ])
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def cov(mode):
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pass
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cov(mode)
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return mode |