mirror of https://github.com/efabless/caravel.git
129 lines
5.0 KiB
ReStructuredText
129 lines
5.0 KiB
ReStructuredText
FLASH_CORE
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==========
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Register Listing for FLASH_CORE
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-------------------------------
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+------------------------------------------------------------------+-------------------------------------------------+
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| Register | Address |
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+==================================================================+=================================================+
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| :ref:`FLASH_CORE_MMAP_DUMMY_BITS <FLASH_CORE_MMAP_DUMMY_BITS>` | :ref:`0xf0001800 <FLASH_CORE_MMAP_DUMMY_BITS>` |
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+------------------------------------------------------------------+-------------------------------------------------+
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| :ref:`FLASH_CORE_MASTER_CS <FLASH_CORE_MASTER_CS>` | :ref:`0xf0001804 <FLASH_CORE_MASTER_CS>` |
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+------------------------------------------------------------------+-------------------------------------------------+
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| :ref:`FLASH_CORE_MASTER_PHYCONFIG <FLASH_CORE_MASTER_PHYCONFIG>` | :ref:`0xf0001808 <FLASH_CORE_MASTER_PHYCONFIG>` |
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+------------------------------------------------------------------+-------------------------------------------------+
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| :ref:`FLASH_CORE_MASTER_RXTX <FLASH_CORE_MASTER_RXTX>` | :ref:`0xf000180c <FLASH_CORE_MASTER_RXTX>` |
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+------------------------------------------------------------------+-------------------------------------------------+
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| :ref:`FLASH_CORE_MASTER_STATUS <FLASH_CORE_MASTER_STATUS>` | :ref:`0xf0001810 <FLASH_CORE_MASTER_STATUS>` |
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+------------------------------------------------------------------+-------------------------------------------------+
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FLASH_CORE_MMAP_DUMMY_BITS
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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`Address: 0xf0001800 + 0x0 = 0xf0001800`
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.. wavedrom::
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:caption: FLASH_CORE_MMAP_DUMMY_BITS
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{
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"reg": [
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{"name": "mmap_dummy_bits[7:0]", "bits": 8},
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{"bits": 24},
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], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1}
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}
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FLASH_CORE_MASTER_CS
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^^^^^^^^^^^^^^^^^^^^
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`Address: 0xf0001800 + 0x4 = 0xf0001804`
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.. wavedrom::
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:caption: FLASH_CORE_MASTER_CS
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{
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"reg": [
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{"name": "master_cs", "bits": 1},
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{"bits": 31},
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], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
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}
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FLASH_CORE_MASTER_PHYCONFIG
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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`Address: 0xf0001800 + 0x8 = 0xf0001808`
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SPI PHY settings.
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.. wavedrom::
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:caption: FLASH_CORE_MASTER_PHYCONFIG
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{
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"reg": [
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{"name": "len", "bits": 8},
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{"name": "width", "bits": 4},
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{"bits": 4},
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{"name": "mask", "bits": 8},
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{"bits": 8}
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], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
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}
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+---------+-------+-----------------------------------------------------------------------------+
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| Field | Name | Description |
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+=========+=======+=============================================================================+
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| [7:0] | LEN | SPI Xfer length (in bits). |
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+---------+-------+-----------------------------------------------------------------------------+
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| [11:8] | WIDTH | SPI Xfer width (1/2/4/8). |
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+---------+-------+-----------------------------------------------------------------------------+
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| [23:16] | MASK | SPI DQ output enable mask (set bits to ``1`` to enable output drivers on DQ |
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| | | lines). |
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+---------+-------+-----------------------------------------------------------------------------+
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FLASH_CORE_MASTER_RXTX
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^^^^^^^^^^^^^^^^^^^^^^
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`Address: 0xf0001800 + 0xc = 0xf000180c`
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.. wavedrom::
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:caption: FLASH_CORE_MASTER_RXTX
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{
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"reg": [
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{"name": "master_rxtx[31:0]", "bits": 32}
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], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1}
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}
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FLASH_CORE_MASTER_STATUS
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^^^^^^^^^^^^^^^^^^^^^^^^
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`Address: 0xf0001800 + 0x10 = 0xf0001810`
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.. wavedrom::
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:caption: FLASH_CORE_MASTER_STATUS
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{
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"reg": [
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{"name": "tx_ready", "bits": 1},
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{"name": "rx_ready", "bits": 1},
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{"bits": 30}
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], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
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}
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+-------+----------+-----------------------+
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| Field | Name | Description |
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+=======+==========+=======================+
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| [0] | TX_READY | TX FIFO is not full. |
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+-------+----------+-----------------------+
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| [1] | RX_READY | RX FIFO is not empty. |
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+-------+----------+-----------------------+
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