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caravel
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caravel/verilog
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Tim Edwards bd6af6dddc Modified all of the Makefiles to better handle the GL netlist simulations, 
which is now done through setting an environment variable to point to the
location of the management SoC wrapper.  Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt.  Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
 		2021-12-03 17:13:53 -05:00
..
dv Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
gl Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
rtl Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00