mirror of https://github.com/efabless/caravel.git
23 lines
312 B
Verilog
23 lines
312 B
Verilog
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module \$_ALDFF_PN_ (D, C, L, AD, Q);
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input D, C, L, AD;
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output reg Q;
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wire RN, SN;
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wire L_N;
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\$_OR_ R_NAND ( .Y(RN), .A(L), .B(AD) );
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\$_NOT_ NAND_NOT ( .A(L), .Y(L_N));
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\$_NAND_ S_NAND ( .Y(SN), .A(L_N), .B(AD) );
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\$_DFFSR_PNN_ SRFF (.C(C),
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.S(SN),
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.R(RN),
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.D(D),
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.Q(Q)
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);
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endmodule
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