mirror of https://github.com/efabless/caravel.git
109 lines
2.7 KiB
Verilog
109 lines
2.7 KiB
Verilog
module gpio_logic_high (gpio_logic1,
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vccd1,
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vssd1);
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output gpio_logic1;
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input vccd1;
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input vssd1;
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sky130_fd_sc_hd__decap_4 FILLER_0_3 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__fill_1 FILLER_0_7 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 FILLER_0_9 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__fill_1 FILLER_1_11 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_8 FILLER_1_3 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_4 FILLER_2_3 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__fill_1 FILLER_2_7 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 FILLER_2_9 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_6 FILLER_3_3 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_4 FILLER_4_3 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__fill_1 FILLER_4_7 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 FILLER_4_9 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(vssd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 (.VGND(vssd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 (.VGND(vssd1),
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.VPWR(vccd1));
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sky130_fd_sc_hd__conb_1 gpio_logic_high (.HI(gpio_logic1),
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.VGND(vssd1),
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.VNB(vssd1),
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.VPB(vccd1),
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.VPWR(vccd1));
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endmodule
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