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riscv
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caravel
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https://github.com/efabless/caravel.git
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95cca2dec0
caravel
/
verilog
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M0stafaRady
95cca2dec0
optimize bitbang tests
2022-10-12 16:06:02 -07:00
..
dv
optimize bitbang tests
2022-10-12 16:06:02 -07:00
gl
~ regenerate chip_io netlist to fix missing power pins from constant blocks
2022-10-12 11:40:05 -07:00
rtl
fix bug of wrapper ack
2022-10-11 06:02:44 -07:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00