Tim Edwards d4b4b7abb8 Fixed one bad error in clock_div which had been done without my ... knowledge and which went undetected since before MPW-one. Modified the "pll" and "sysctrl" testbenches so that they run and measure something useful. Both exercise the clock monitoring on GPIO outputs functions. The PLL test also runs the digital locked loop (behavioral verilog). The PLL test overlaps sysctrl, but "pll" cannot be run on gate level verilog, whereas "sysctrl" can.		2021-12-06 21:37:51 -05:00
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caravel	Fixed one bad error in clock_div which had been done without my	2021-12-06 21:37:51 -05:00
wb_utests	Corrected the two failing testbenches (which needed fixing because	2021-10-28 22:20:46 -04:00