Tim Edwards 489bddcf98 Two more changes: (1) Correction to chip_io_alt.v RTL verilog to ... match what was done earlier on chip_io.v, and (2) Corrected a set of four labels in chip_io_alt.mag which had been rotated, causing an error in LVS.		2021-12-07 17:16:44 -05:00
..
dv	Fixed one bad error in clock_div which had been done without my	2021-12-06 21:37:51 -05:00
gl	Corrected an error in verilog/gl/chip_io_alt.v, which was missing	2021-12-07 10:06:35 -05:00
rtl	Two more changes: (1) Correction to chip_io_alt.v RTL verilog to	2021-12-07 17:16:44 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00