Tim Edwards ac209d2397 Corrected a bunch of typos (different signal names used in the ... same file), errors (buffer output pin name, power supplies not passed at the top level). Corrected a major error that prevented the use of the buffers in simulation, so this was not previously verified by simulation. The buffering has now been properly verified.		2022-10-14 10:51:29 -04:00
..
dv	added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list	2022-10-10 06:23:47 -07:00
gl	~ regenerate chip_io netlist to fix missing power pins from constant blocks	2022-10-12 11:40:05 -07:00
rtl	Corrected a bunch of typos (different signal names used in the	2022-10-14 10:51:29 -04:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00