mirror of https://github.com/efabless/caravel.git
115 lines
6.3 KiB
Python
115 lines
6.3 KiB
Python
import json
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import cocotb
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from cocotb.triggers import Timer, RisingEdge, ReadOnly
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from cocotb_bus.monitors import Monitor
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from cocotb.log import SimLogFormatter, SimTimeContextFilter
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from cocotb.binary import BinaryValue
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from math import ceil
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from wb_models.housekeepingWB.HKmonitor import HKmonitor
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from wb_models.housekeepingWB.HKSPImonitor import HKSPImonitor
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from wb_models.housekeepingWB.HKSPImonitor import CSBmonitor
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from wb_models.housekeepingWB.HK_models import HK_models
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from cocotb_bus.scoreboard import Scoreboard
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import logging
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import fnmatch
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import copy
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from cocotb.result import TestFailure
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from common import Macros
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class HK_whiteBox:
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def __init__(self,dut,loggers=False):
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self.dut = dut
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self.hk_hdl = dut.uut.housekeeping
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# self.hkspi_hdl = dut.uut.housekeeping.hkspi
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self.clk = self.dut.uut.mprj_clock
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self.reset = self.dut.uut.resetb
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self.logger = loggers
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self.load_js()
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self.setupModels()
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self.Monitors()
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cocotb.scheduler.add(self.reg_model_sb())
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"""load json models"""
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def load_js(self):
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with open('wb_models/housekeepingWB/housekeepingIF.json') as f:
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self.interface = json.load(f)
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with open('wb_models/housekeepingWB/HK_regs.json') as f:
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self.reg_model = json.load(f)
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self.output_if = copy.deepcopy(self.interface['outputs'])
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""""method to add the housekeeping monitors"""
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def Monitors(self):
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inputs = self.interface['inputs']
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outputs = self.interface['outputs']
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# wishbone
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wishbone_mon_i = HKmonitor(f"HKinputsMonitorwishbone",self.hk_hdl,inputs['wishbone'],self.clk,self.reset,self.logger,callback=self.wb_models.wishbone_model)
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wishbone_mon_o = HKmonitor(f"HKoutputsMonitorwishbone",self.hk_hdl,outputs['wishbone'],self.clk,self.reset,self.logger)
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wishbone_sb = Scoreboard(SB_name("wishbone_sb"),fail_immediately=False)
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wishbone_sb.add_interface(wishbone_mon_o, self.wb_models.exp_out_wb)
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# system
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system_mon_i = HKmonitor(f"HKinputsMonitorsystem",self.hk_hdl,inputs['system'],self.clk,self.reset,self.logger,callback=self.wb_models.system_model)
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# UART
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UART_mon_i = HKmonitor(f"HKinputsMonitorUART",self.hk_hdl,inputs['UART'],self.clk,self.reset,self.logger,callback=self.wb_models.UART_model)
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UART_mon_o = HKmonitor(f"HKoutputsMonitorUART",self.hk_hdl,outputs['UART'],self.clk,self.reset,self.logger)
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UART_sb = Scoreboard(SB_name("UART_sb"),fail_immediately=False)
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UART_sb.add_interface(UART_mon_o, self.wb_models.exp_out_uart_rx)
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# debug
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debug_mon_i = HKmonitor(f"HKinputsMonitordebug",self.hk_hdl,inputs['debug'],self.clk,self.reset,self.logger,callback=self.wb_models.debug_model)
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debug_mon_o = HKmonitor(f"HKoutputsMonitordebug",self.hk_hdl,outputs['debug'],self.clk,self.reset,self.logger)
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debug_sb = Scoreboard(SB_name("debug_sb"),fail_immediately=False)
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debug_sb.add_interface(debug_mon_o, self.wb_models.exp_out_debug)
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# SPI
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SPI_mon_i = HKSPImonitor(f"HKinputsMonitorSPI",self.hk_hdl,inputs['SPI'],self.clk,self.reset,self.logger,callback=self.wb_models.spi_model)
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SPI_mon_o = HKSPImonitor(f"HKoutputsMonitorSPI",self.hk_hdl,outputs['SPI'],self.clk,self.reset,self.logger,input=False)
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CSBmonitor(f"HKCSBmonitor",self.hk_hdl,outputs['SPI'],self.clk,self.reset,False,callback=self.wb_models.reset_spi_vals)
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SPI_sb = Scoreboard(SB_name("SPI_sb"),fail_immediately=False)
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SPI_sb.add_interface(SPI_mon_o, self.wb_models.exp_out_spi)
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"""initialize all models needed"""
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def setupModels(self):
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with open('wb_models/housekeepingWB/HK_regs.json') as f:
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self.reg_model = json.load(f)
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self.wb_models = HK_models(self.reg_model,self.output_if,self.hk_hdl)
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"""scoreboard for register model check the reg model with RTL every clock"""
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async def reg_model_sb(self):
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while True:
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await RisingEdge(self.clk)
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for key,memory_block in self.reg_model.items():
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if fnmatch.fnmatch(key, "_*"):
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continue
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for reg_shift,reg in memory_block.items():
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for field in reg:
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if reg_shift == "base_addr":
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continue
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RTL_reg_name = field[1]
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if RTL_reg_name == None:
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cocotb.log.debug(f"[HK_whiteBox][reg_model_sb] register {field[1]} in {key} doesn't have a RTL register")
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continue
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if isinstance(field[1],list):
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RTL_name = field[1][0]
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first_index = int(field[1][1])
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second_index= int(field[1][2])
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if Macros['GL']:
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if RTL_name in ["mfgr_id","prod_id","mask_rev","mgmt_gpio_data"]: continue #TODO: change with SDF only
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if Macros['GL']:
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if fnmatch.fnmatch (RTL_name,"gpio_configure*"): continue #TODO: update gpio_configure and mgmt_gpio_data to get each bit in the SDF case
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RTL_reg_path = self.hk_hdl._id(RTL_name,False)
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size = RTL_reg_path.value.n_bits-1
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RTL_reg_val = RTL_reg_path.value[size-first_index:size-second_index]
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else :
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if field[1] in ["pwr_ctrl_out"]: continue #TODO: delete when reset value is spicified
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RTL_reg_path = self.hk_hdl._id(field[1],False)
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RTL_reg_val = RTL_reg_path.value
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if (RTL_reg_val.integer != field[6]):
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cocotb.log.error(f'[HK_whiteBox][reg_model_sb] mismatch in register {field[1]} in {key} expected val = {int(field[6])} actual val = {int(RTL_reg_val.binstr,2)} ' )
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else:
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cocotb.log.debug(f'[HK_whiteBox][reg_model_sb] match in register {field[1]} in {key} expected val = {field[6]} actual val = {RTL_reg_val.integer} ' )
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class SB_name:
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def __init__(self,name) -> None:
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self._name=name
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