mirror of https://github.com/efabless/caravel.git
317 lines
16 KiB
Python
317 lines
16 KiB
Python
import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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from cpu import RiskV
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from defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from caravel import GPIO_MODE
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from common import Macros
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reg = Regs()
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@cocotb.test()
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@repot_test
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async def bitbang_cpu_all_o(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=2075459)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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await wait_reg1(cpu,caravelEnv,0xFF)
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cocotb.log.info("[TEST] finish configuring using bitbang")
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i= 0x20
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for j in range(5):
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await wait_reg2(cpu,caravelEnv,37-j)
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cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
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if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
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cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
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await wait_reg2(cpu,caravelEnv,0)
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if caravelEnv.monitor_gpio((37,4)).integer != 0:
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cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
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i = i >> 1
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i |= 0x20
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i= 0x80000000
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for j in range(32):
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await wait_reg2(cpu,caravelEnv,32-j)
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cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
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if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
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cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
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if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
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cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
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await wait_reg2(cpu,caravelEnv,0)
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if caravelEnv.monitor_gpio((37,4)).integer != 0:
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cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
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i = i >> 1
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i |= 0x80000000
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await ClockCycles(caravelEnv.clk, 10)
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@cocotb.test()
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@repot_test
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async def bitbang_cpu_all_10(dut):
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caravelEnv = await test_configure(dut,timeout_cycles=2863378)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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uut = dut.uut
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await wait_reg1(cpu,caravelEnv,0xFF)
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gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
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gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
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type = True # type of shifting 01 or 10
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for gpio in gpios_l:
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shift(uut._id(gpio,False),type)
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type = not type
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type = True # type of shifting 01 or 10
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for gpio in reversed(gpios_h):
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shift(uut._id(gpio,False),type)
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type = not type
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def shift(gpio,shift_type):
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if shift_type:
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bits = "0101010101010"
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else:
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bits = "1010101010101"
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fail = False
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cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
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for i in range(13):
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if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
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fail = True
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cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
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if not fail:
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cocotb.log.info(f"[TEST] gpio {gpio} passed")
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@cocotb.test()
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@repot_test
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async def bitbang_cpu_all_01(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=2863378)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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uut = dut.uut
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await wait_reg1(cpu,caravelEnv,0xFF)
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gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
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gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
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type = False # type of shifting 01 or 10
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for gpio in gpios_l:
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shift(uut._id(gpio,False),type)
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type = not type
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type = False # type of shifting 01 or 10
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for gpio in reversed(gpios_h):
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shift(uut._id(gpio,False),type)
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type = not type
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@cocotb.test()
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@repot_test
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async def bitbang_cpu_all_0011(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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uut = dut.uut
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await wait_reg1(cpu,caravelEnv,0xFF)
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gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
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gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
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type = 0 # type of shifting 01 or 10
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for gpio in gpios_l:
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shift_2(uut._id(gpio,False),type)
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type = (type + 1) %4
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type = 0 # type of shifting 01 or 10
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for gpio in reversed(gpios_h):
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shift_2(uut._id(gpio,False),type)
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type = (type + 1) %4
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@cocotb.test()
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@repot_test
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async def bitbang_cpu_all_1100(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=10000000000)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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uut = dut.uut
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await wait_reg1(cpu,caravelEnv,0xFF)
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gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
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gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
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type = 2 # type of shifting 01 or 10
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for gpio in gpios_l:
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shift_2(uut._id(gpio,False),type)
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type = (type + 1) %4
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type = 2 # type of shifting 01 or 10
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for gpio in reversed(gpios_h):
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shift_2(uut._id(gpio,False),type)
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type = (type + 1) %4
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def shift_2(gpio,shift_type):
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if shift_type == 0:
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bits = "1001100110011"
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elif shift_type == 1:
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bits = "1100110011001"
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elif shift_type == 2:
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bits = "0110011001100"
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elif shift_type == 3:
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bits = "0011001100110"
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fail = False
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cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
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for i in range(13):
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if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
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fail = True
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cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
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if not fail:
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cocotb.log.info(f"[TEST] gpio {gpio} passed")
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@cocotb.test()
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@repot_test
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async def bitbang_cpu_all_i(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=1691295)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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uut = dut.uut
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await wait_reg1(cpu,caravelEnv,0xAA)
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cocotb.log.info(f"[TEST] configuration finished")
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data_in = 0x8F66FD7B
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cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
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caravelEnv.drive_gpio_in((31,0),data_in)
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await wait_reg1(cpu,caravelEnv,0xBB)
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]")
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data_in = 0xFFA88C5A
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cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
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caravelEnv.drive_gpio_in((31,0),data_in)
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await wait_reg1(cpu,caravelEnv,0xCC)
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]")
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data_in = 0xC9536346
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cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
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caravelEnv.drive_gpio_in((31,0),data_in)
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await wait_reg2(cpu,caravelEnv,0xFF)
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cocotb.log.info(f"[TEST] finish")
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"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as output."""
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@cocotb.test()
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@repot_test
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async def bitbang_spi_o(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=639757)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured
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#Configure all as output except reg_mprj_io_3
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32
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await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33
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await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34
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await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 1 and 36
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await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 0 and 37
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await load_spi(caravelEnv) # load
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cpu.write_debug_reg2_backdoor(0xFF)
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cocotb.log.info("[TEST] finish configuring using bitbang")
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i= 0x20
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for j in range(5):
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await wait_reg2(cpu,caravelEnv,37-j)
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cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}')
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if caravelEnv.monitor_gpio((37,5)).integer != i << 27:
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cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 28)}')
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await wait_reg2(cpu,caravelEnv,0)
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if caravelEnv.monitor_gpio((37,5)).integer != 0:
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cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
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i = i >> 1
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i |= 0x20
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i= 0x80000000
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for j in range(32):
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await wait_reg2(cpu,caravelEnv,32-j)
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cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}')
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if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
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cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
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if caravelEnv.monitor_gpio((31,5)).integer != i>>5 :
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cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
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await wait_reg2(cpu,caravelEnv,0)
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if caravelEnv.monitor_gpio((37,5)).integer != 0:
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cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
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i = i >> 1
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i |= 0x80000000
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await ClockCycles(caravelEnv.clk, 10)
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"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as input."""
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@cocotb.test()
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@repot_test
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async def bitbang_spi_i(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=56703)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured
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#Configure all as output except reg_mprj_io_3
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 18 and 19
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 17 and 20
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 16 and 21
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 15 and 22
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 14 and 23
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 13 and 24
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 12 and 25
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 11 and 26
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 10 and 27
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 9 and 28
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 8 and 29
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 7 and 30
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 6 and 31
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 5 and 32
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 4 and 33
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 3 and 34
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 2 and 35
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 1 and 36
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await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 0 and 37
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await load_spi(caravelEnv) # load
|
|
|
|
await wait_reg1(cpu,caravelEnv,0xAA)
|
|
cocotb.log.info("[TEST] finish configuring using bitbang")
|
|
data_in = 0x8F66FD7B
|
|
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
|
caravelEnv.drive_gpio_in((31,0),data_in)
|
|
await wait_reg1(cpu,caravelEnv,0xBB)
|
|
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]")
|
|
data_in = 0xFFA88C5A
|
|
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
|
caravelEnv.drive_gpio_in((31,0),data_in)
|
|
await wait_reg1(cpu,caravelEnv,0xCC)
|
|
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]")
|
|
data_in = 0xC9536346
|
|
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
|
caravelEnv.drive_gpio_in((31,0),data_in)
|
|
|
|
await wait_reg2(cpu,caravelEnv,0xFF)
|
|
cocotb.log.info(f"[TEST] finish") |