mirror of https://github.com/efabless/caravel.git
107 lines
2.8 KiB
YAML
107 lines
2.8 KiB
YAML
- status: 0 - openlane design prep
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runtime_s: 1.75
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runtime_ts: 0h0m1s750ms
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- status: 1 - synthesis - yosys
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runtime_s: 1.19
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runtime_ts: 0h0m1s187ms
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- status: 2 - sta - openroad
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runtime_s: 0.45
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runtime_ts: 0h0m0s446ms
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- status: 3 - floorplan initialization - openroad
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runtime_s: 0.54
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runtime_ts: 0h0m0s539ms
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- status: 4 - io_place - openlane
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runtime_s: 0.3
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runtime_ts: 0h0m0s299ms
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- status: 5 - tap/decap insertion - openroad
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runtime_s: 0.42
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runtime_ts: 0h0m0s422ms
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- status: 6 - pdn generation - openroad
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runtime_s: 0.44
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runtime_ts: 0h0m0s437ms
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- status: 7 - random global placement - openlane
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runtime_s: 0.31
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runtime_ts: 0h0m0s306ms
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- status: 8 - detailed placement - openroad
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runtime_s: 0.47
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runtime_ts: 0h0m0s466ms
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- status: 9 - detailed placement - openroad
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runtime_s: 0.46
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runtime_ts: 0h0m0s463ms
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- status: 11 - write verilog - openroad
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runtime_s: 0.39
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runtime_ts: 0h0m0s392ms
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- status: 11 - global routing - openroad
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runtime_s: 0.49
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runtime_ts: 0h0m0s492ms
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- status: 12 - fill insertion - openroad
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runtime_s: 0.46
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runtime_ts: 0h0m0s464ms
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- status: 13 - detailed_routing - openroad
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runtime_s: 0.73
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runtime_ts: 0h0m0s726ms
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- status: 14 - wire lengths - openlane
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runtime_s: 0.25
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runtime_ts: 0h0m0s251ms
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- status: 15 - parasitics extraction - openroad
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runtime_s: 0.44
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runtime_ts: 0h0m0s441ms
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- status: 16 - sta - openroad
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runtime_s: 1.49
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runtime_ts: 0h0m1s492ms
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- status: 17 - parasitics extraction - openroad
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runtime_s: 0.43
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runtime_ts: 0h0m0s429ms
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- status: 18 - sta - openroad
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runtime_s: 1.5
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runtime_ts: 0h0m1s499ms
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- status: 19 - parasitics extraction - openroad
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runtime_s: 0.43
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runtime_ts: 0h0m0s428ms
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- status: 20 - sta - openroad
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runtime_s: 1.51
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runtime_ts: 0h0m1s510ms
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- status: 21 - sta - openroad
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runtime_s: 0.38
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runtime_ts: 0h0m0s377ms
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- status: 22 - ir drop report - openroad
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runtime_s: 0.41
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runtime_ts: 0h0m0s413ms
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- status: 23 - gdsii - magic
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runtime_s: 1.3
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runtime_ts: 0h0m1s296ms
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- status: 24 - gdsii - klayout
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runtime_s: 0.42
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runtime_ts: 0h0m0s421ms
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- status: 25 - xor - klayout
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runtime_s: 0.33
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runtime_ts: 0h0m0s334ms
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- status: 26 - spice extraction - magic
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runtime_s: 0.37
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runtime_ts: 0h0m0s370ms
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- status: 28 - write verilog - openroad
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runtime_s: 0.4
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runtime_ts: 0h0m0s403ms
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- status: 28 - write powered verilog - openlane
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runtime_s: 0.51
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runtime_ts: 0h0m0s514ms
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- status: 29 - lvs - netgen
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runtime_s: 0.09
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runtime_ts: 0h0m0s93ms
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- status: 30 - drc - magic
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runtime_s: 1.05
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runtime_ts: 0h0m1s52ms
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- status: 31 - antenna check - openroad
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runtime_s: 0.45
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runtime_ts: 0h0m0s453ms
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- status: 32 - erc - circuit validity checker
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runtime_s: 0.13
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runtime_ts: 0h0m0s131ms
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---
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- status: routed
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runtime_s: 11.0
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runtime_ts: 0h0m11s0ms
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- status: flow completed
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runtime_s: 26.0
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runtime_ts: 0h0m26s0ms
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