mirror of https://github.com/efabless/caravel.git
70 lines
2.1 KiB
Tcl
70 lines
2.1 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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# OR COMMIT: 182e733faa149c80f36cfd2198a83dcdeb7853ea
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set ::env(DESIGN_NAME) "housekeeping"
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set ::env(ROUTING_CORES) 36
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set ::env(RUN_KLAYOUT) 0
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set ::env(VERILOG_FILES) "\
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$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
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$::env(DESIGN_DIR)/../../verilog/rtl/housekeeping_spi.v\
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$::env(DESIGN_DIR)/../../verilog/rtl/housekeeping.v"
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set ::env(CLOCK_PORT) "wb_clk_i"
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set ::env(CLOCK_NET) "$::env(CLOCK_PORT) csclk mgmt_gpio_in\[4\]"
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set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/template/housekeeping.def
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set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
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## Synthesis
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set ::env(NO_SYNTH_CELL_LIST) $::env(DESIGN_DIR)/no_synth.list
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set ::env(SYNTH_STRATEGY) "AREA 0"
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set ::env(SYNTH_MAX_FANOUT) 7
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## Floorplan
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 300.230 550.950"
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set ::env(DPL_CELL_PADDING) 2
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set ::env(GPL_CELL_PADDING) 2
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## Routing
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set ::env(GRT_ADJUSTMENT) 0.06
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set ::env(GRT_LAYER_ADJUSTMENTS) "0.99,0.2,0,0,0,0"
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set ::env(GRT_OVERFLOW_ITERS) 100
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set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.17
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## Placement
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set ::env(PL_TARGET_DENSITY) 0.5
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set ::env(GRT_ALLOW_CONGESTION) 0
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set ::env(CLOCK_TREE_SYNTH) 1
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) .17
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set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "30"
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) "3"
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set ::env(GRT_ANT_ITERS) "7"
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