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__uprj_analog_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__uprj_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__user_analog_project_wrapper.v
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cocotb - updates related to enable simulating caraval using iverilog (#320)
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2022-10-21 07:43:34 -07:00 |
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__user_project_gpio_example.v
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Add gpio_all_bidir_user test
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2022-10-10 15:59:20 -07:00 |
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__user_project_la_example.v
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add test la test
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2022-10-08 06:25:26 -07:00 |
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__user_project_wrapper.v
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fix bug of wrapper ack
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2022-10-11 06:02:44 -07:00 |
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buff_flash_clkrst.v
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connected rest of buffers to power
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2022-10-17 01:15:46 +02:00 |
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caravan.v
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fixed documentation for gpio's used in caravan
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2022-11-11 08:22:20 -08:00 |
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caravan_netlists.v
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Added buffers to the top level, inside a macro called
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2022-10-13 13:29:27 -04:00 |
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caravan_openframe.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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caravan_power_routing.v
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Caravan redesign (#321)
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2022-10-21 07:37:41 -07:00 |
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caravel.v
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Move decleration of some signal in caravel.v to fix error in iverilog
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2022-10-20 06:26:55 -07:00 |
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caravel_clocking.v
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Changed the synchronized reset to occur on the clock falling edge
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2021-12-02 14:26:59 -05:00 |
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caravel_logo.v
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reharden: caravel
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2022-10-16 15:44:27 -07:00 |
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caravel_motto.v
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reharden: caravel
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2022-10-16 15:44:27 -07:00 |
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caravel_netlists.v
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Added buffers to the top level, inside a macro called
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2022-10-13 13:29:27 -04:00 |
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caravel_openframe.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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caravel_power_routing.v
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reharden!: caravel
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2022-10-10 04:51:05 -07:00 |
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chip_io.v
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some rtl changes
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2022-10-10 05:13:48 -07:00 |
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chip_io_alt.v
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Caravan redesign (#321)
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2022-10-21 07:37:41 -07:00 |
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clock_div.v
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Fixed one bad error in clock_div which had been done without my
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2021-12-06 21:37:51 -05:00 |
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constant_block.v
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Modified the GPIO control block to buffer the constant high/low outputs.
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2022-09-20 17:49:08 -04:00 |
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copyright_block.v
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reharden: caravel
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2022-10-16 15:44:27 -07:00 |
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debug_regs.v
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Add gpio_all_o_user test
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2022-10-09 07:53:25 -07:00 |
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defines.v
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Update storage testbench to work with one 2K block
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2021-11-12 17:14:21 +02:00 |
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digital_pll.v
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reharden!: digital_pll
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2022-10-17 10:56:01 -07:00 |
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digital_pll_controller.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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gpio_control_block.v
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add sky130_fd_sc_hd__macro_sparecell inside gpio_control_block rtl
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2022-10-10 05:24:25 -07:00 |
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gpio_defaults_block.v
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Implemented a system for setting the GPIO power-on defaults through
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2021-10-23 17:18:30 -04:00 |
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gpio_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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gpio_signal_buffering.v
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bugfix: remove extra comma after the last port in the decaps declaration
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2022-11-07 13:00:00 +02:00 |
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gpio_signal_buffering_alt.v
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bugfix: remove extra comma after the last port in the decaps declaration
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2022-11-07 13:00:00 +02:00 |
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housekeeping.v
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Syntax changes that are non-functional from a synthesis perspective. (#324)
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2022-10-21 10:10:20 -07:00 |
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housekeeping_spi.v
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Syntax changes that are non-functional from a synthesis perspective. (#324)
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2022-10-21 10:10:20 -07:00 |
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mgmt_protect.v
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fix some typos on mgmt_protect
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2022-10-05 03:27:46 -07:00 |
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mgmt_protect_hv.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj2_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj_io.v
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Fix typo at mprj_io (#168)
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2022-10-10 12:11:05 -07:00 |
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mprj_logic_high.v
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Revised the management protect block to include protections against
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2021-10-27 19:36:43 -04:00 |
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open_source.v
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reharden: caravel
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2022-10-16 15:44:27 -07:00 |
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pads.v
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Modified the GPIO control block to buffer the constant high/low outputs.
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2022-09-20 17:49:08 -04:00 |
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ring_osc2x13.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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simple_por.v
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Modified simple_por.v RTL to avoid the wire declaration that "cvc"
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2021-12-08 12:16:19 -05:00 |
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spare_logic_block.v
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Revised the spare logic block to make sure that all inputs are
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2021-11-24 09:34:52 -05:00 |
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user_defines.v
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Fixes the user defines configuration values for pullup and pulldown
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2022-11-16 09:36:01 -05:00 |
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user_id_programming.v
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Implemented a system for setting the GPIO power-on defaults through
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2021-10-23 17:18:30 -04:00 |
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user_id_textblock.v
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reharden: caravel
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2022-10-16 15:44:27 -07:00 |
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xres_buf.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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