mirror of https://github.com/efabless/caravel.git
68 lines
2.4 KiB
Python
68 lines
2.4 KiB
Python
import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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from interfaces.cpu import RiskV
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from interfaces.defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from interfaces.caravel import GPIO_MODE
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from tests.housekeeping.housekeeping_spi.spi_access_functions import *
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reg = Regs()
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@cocotb.test()
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@repot_test
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async def cpu_reset(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=34823)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start cpu_reset test")
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# wait for CPU to write 5 at debug_reg1
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while True:
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if cpu.read_debug_reg1() == 5:
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cocotb.log.info("[TEST] debug reg 1 = 5" )
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break
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await ClockCycles(caravelEnv.clk,1)
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# put the cpu under reset using spi
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cocotb.log.info("[TEST] asserting cpu reset register using SPI")
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await write_reg_spi(caravelEnv,0xb,1)
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await ClockCycles(caravelEnv.clk,1000)
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if cpu.read_debug_reg1() == 0:
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cocotb.log.info("[TEST] asserting cpu reset register using SPI successfully rest the cpu")
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else:
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cocotb.log.error("[TEST] asserting cpu reset register using SPI successfully doesn't rest the cpu")
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cocotb.log.info("[TEST] deasserting cpu reset register using SPI")
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await write_reg_spi(caravelEnv,0xb,0)
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watchdog = 12000
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while True:
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if cpu.read_debug_reg1() == 5:
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cocotb.log.info("[TEST] deasserting cpu reset register using SPI wakes the cpu up" )
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break
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watchdog -=1
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if watchdog <0:
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cocotb.log.error("[TEST] deasserting cpu reset register using SPI doesn't wake the cpu up" )
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break
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await ClockCycles(caravelEnv.clk,1)
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cocotb.log.info("[TEST] asserting cpu reset register using firmware")
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cpu.write_debug_reg2_backdoor(0xAA)
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await ClockCycles(caravelEnv.clk,10000)
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watchdog = 8000
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while True:
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if cpu.read_debug_reg1() == 0:
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cocotb.log.info("[TEST] asserting cpu reset register using firmware successfully rest the cpu" )
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break
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watchdog -=1
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if watchdog <0:
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cocotb.log.error("[TEST] asserting cpu reset register using firmware successfully doesn't rest the cpu" )
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break
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await ClockCycles(caravelEnv.clk,100)
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