mirror of https://github.com/efabless/caravel.git
47 lines
3.2 KiB
Plaintext
47 lines
3.2 KiB
Plaintext
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
|
|
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
|
|
cf40562ae6508f3dc5e81420e31f7b5886dc3c8f verilog/rtl/__user_analog_project_wrapper.v
|
|
79cdb50a7dd60f69b63c0b6440b0dea35386387d verilog/rtl/__user_project_gpio_example.v
|
|
5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v
|
|
cc82a78753f5f5d0a1519bd81adbcff8a4296d91 verilog/rtl/__user_project_wrapper.v
|
|
3c8c04f53b2848dc46132cda82c614e06e56571b verilog/rtl/buff_flash_clkrst.v
|
|
7c2c90674cd597f4b0b6dc18b8b4bc28c7471faa verilog/rtl/caravan.v
|
|
06e92151b5928e3f28e30a5cde76f7dd6530ed91 verilog/rtl/caravan_netlists.v
|
|
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
|
|
b532b4c6315c29fd19fe38ac221b6fc41e6f5ecb verilog/rtl/caravan_power_routing.v
|
|
b38b8911910265a96d8248095964a5ee8139820b verilog/rtl/caravel.v
|
|
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
|
|
625c9f974f1a3c9bd2eca5449a89a7bfb8f69fe8 verilog/rtl/caravel_logo.v
|
|
1bbaa93405d4cb51429eacea4da40014231b11ed verilog/rtl/caravel_motto.v
|
|
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
|
|
d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
|
|
bc1e961e41d1d3a383a018279a08bf4108911f53 verilog/rtl/chip_io.v
|
|
f2242e1f295ee5efeacea51698f706a2cfd97c28 verilog/rtl/chip_io_alt.v
|
|
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
|
|
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
|
|
58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
|
|
653b230c7cbf092a6210ba7820bc942f312e53f3 verilog/rtl/debug_regs.v
|
|
2a7b5d508735fd485f8adcb3f8766ea3830091c2 verilog/rtl/digital_pll.v
|
|
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
|
00d2c61e4f424dfce3635f96a1c1bfdeaf7d0cf8 verilog/rtl/gpio_control_block.v
|
|
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
|
|
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
|
406b6eba38e0a7e8ff561dc4e5395dbefc9c175c verilog/rtl/gpio_signal_buffering.v
|
|
45ea4a2d466d6d70e9e86011a62c1bd3f706ef99 verilog/rtl/gpio_signal_buffering_alt.v
|
|
0dc5b899412a3a3a3a8ccf662bad1056d294f50b verilog/rtl/housekeeping.v
|
|
34c6ab585986a00216c72f2f1fea0e5a8523867b verilog/rtl/housekeeping_spi.v
|
|
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
|
|
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
|
|
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
|
|
c96ba94e5779ea6afe452d89632eaada73e26aab verilog/rtl/mprj_io.v
|
|
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
|
|
5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v
|
|
4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v
|
|
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
|
|
6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
|
|
1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v
|
|
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
|
|
c94f7ed5aa311f005513ace344991c8e6d3d19f5 scripts/set_user_id.py
|
|
98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py
|
|
3210e724c6dc99563af780ff1778fada5b432604 scripts/compositor.py
|