mirror of https://github.com/efabless/caravel.git
34 lines
2.3 KiB
Plaintext
34 lines
2.3 KiB
Plaintext
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
|
|
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
|
|
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
|
|
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
|
|
ad30a2c7df753845db0ea65c1f3387c3e55b8f06 verilog/rtl/caravan.v
|
|
a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v
|
|
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
|
|
0b5b9fc879625af003415776671bc44cdc774470 verilog/rtl/caravel.v
|
|
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
|
|
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
|
|
d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v
|
|
05afc0b0e001335ac940bec43cca0ce2ac55b277 verilog/rtl/chip_io_alt.v
|
|
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
|
|
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
|
|
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
|
3a62ce6627741ec3eaf798a23807ef15c46475a4 verilog/rtl/gpio_control_block.v
|
|
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
|
|
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
|
5469b880904d6dd5d1eba6f026b3582810df412c verilog/rtl/housekeeping.v
|
|
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
|
|
0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v
|
|
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
|
|
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
|
|
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v
|
|
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
|
|
6f490c83d6064c380a3f475823ef97f325d7f6c1 verilog/rtl/pads.v
|
|
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
|
|
6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
|
|
1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v
|
|
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
|
|
905526f5cad188e9bd8625d2d537007f6523e97d scripts/set_user_id.py
|
|
98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py
|
|
3210e724c6dc99563af780ff1778fada5b432604 scripts/compositor.py
|