mirror of https://github.com/efabless/caravel.git
121 lines
5.5 KiB
Tcl
121 lines
5.5 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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# Power nets
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if { ! [info exists ::env(VDD_NET)] } {
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set ::env(VDD_NET) $::env(VDD_PIN)
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}
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if { ! [info exists ::env(GND_NET)] } {
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set ::env(GND_NET) $::env(GND_PIN)
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}
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set ::power_nets $::env(VDD_NET)
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set ::ground_nets $::env(GND_NET)
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if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
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if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
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foreach power_pin $::env(STD_CELL_POWER_PINS) {
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add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
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}
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foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
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add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
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}
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}
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}
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set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
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if { $::env(VDD_NET) == "vdda1" } {
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define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
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add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset 929 -starts_with POWER
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} elseif {$::env(VDD_NET) == "vdda2"} {
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define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
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add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset 932 -starts_with POWER
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} else {
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define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
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add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
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}
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# Adds the standard cell rails if enabled.
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if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
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add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
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add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
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}
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# Adds the core ring if enabled.
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if { $::env(FP_PDN_CORE_RING) == 1 } {
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add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
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-widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
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-spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
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-core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
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add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
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}
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set ::halo [expr min($::env(FP_HORIZONTAL_HALO), $::env(FP_VERTICAL_HALO))]
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# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
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if { $::env(VDD_NET) == "vccd1" } {
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set mprj_logic_high_macro {
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macro mprj_logic_high
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power_pins $::env(VDD_NET)
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ground_pins $::env(GND_NET)
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blockages "met3"
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straps {
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}
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connect {{$::env(FP_PDN_UPPER_LAYER)_PIN_hor $::env(FP_PDN_LOWER_LAYER)}}
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}
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pdngen::specify_grid macro [subst $mprj_logic_high_macro]
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define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)}]
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}
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if { $::env(VDD_NET) == "vccd2" } {
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set mprj2_logic_high_macro {
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macro mprj2_logic_high
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power_pins $::env(VDD_NET)
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ground_pins $::env(GND_NET)
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blockages "met3"
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straps {
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}
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connect {{$::env(FP_PDN_UPPER_LAYER)_PIN_hor $::env(FP_PDN_LOWER_LAYER)}}
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}
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pdngen::specify_grid macro [subst $mprj2_logic_high_macro]
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define_pdn_grid -macro -cells "mprj_logic_high mgmt_protect_hv" -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)}]
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}
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if { $::env(VDD_NET) == "vccd" || $::env(VDD_NET) == "vdda2" || $::env(VDD_NET) == "vdda1" } {
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set mgmt_protect_hv_macro {
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macro mgmt_protect_hv
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power_pins $::env(VDD_NET)
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ground_pins $::env(GND_NET)
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blockages "met3"
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straps {
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}
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connect {{$::env(FP_PDN_UPPER_LAYER)_PIN_hor $::env(FP_PDN_LOWER_LAYER)}}
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}
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pdngen::specify_grid macro [subst $mgmt_protect_hv_macro]
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define_pdn_grid -macro -cells "mprj_logic_high mprj2_logic_high" -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)}]
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}
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# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
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set ::rails_start_with "POWER" ;
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# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
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set ::stripes_start_with "POWER" ; |