mirror of https://github.com/efabless/caravel.git
264 lines
8.3 KiB
Verilog
264 lines
8.3 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*----------------------------------------------------------------------*/
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/* Buffers protecting the management region from the user region. */
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/* This mainly consists of tristate buffers that are enabled by a */
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/* "logic 1" output connected to the user's VCCD domain. This ensures */
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/* that the buffer is disabled and the output high-impedence when the */
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/* user 1.8V supply is absent. */
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/*----------------------------------------------------------------------*/
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/* Because there is no tristate buffer with a non-inverted enable, a */
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/* tristate inverter with non-inverted enable is used in series with */
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/* another (normal) inverter. */
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/*----------------------------------------------------------------------*/
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/* For the sake of placement/routing, one conb (logic 1) cell is used */
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/* for every buffer. */
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/*----------------------------------------------------------------------*/
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/* 10/3/2022: Removed tri-state buffers in favor of AND gates; i.e., */
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/* if the user project is powered down, then the outputs are grounded */
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/* rather than tristated. Other explicitly-referenced gates removed */
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/* with the assumption that all outputs will be buffered as needed by */
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/* the synthesis tools. Therefore the only restrictions needed on the */
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/* synthesis tools is the list of input signals that must not be */
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/* buffered because they are allowed to be floating. */
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/*----------------------------------------------------------------------*/
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module mgmt_protect (
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`ifdef USE_POWER_PINS
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inout vccd,
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inout vssd,
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inout vccd1,
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inout vssd1,
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inout vccd2,
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inout vssd2,
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inout vdda1,
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inout vssa1,
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inout vdda2,
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inout vssa2,
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`endif
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input caravel_clk,
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input caravel_clk2,
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input caravel_rstn,
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input mprj_cyc_o_core,
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input mprj_stb_o_core,
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input mprj_we_o_core,
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input [3:0] mprj_sel_o_core,
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input [31:0] mprj_adr_o_core,
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input [31:0] mprj_dat_o_core,
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input [2:0] user_irq_core,
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output [31:0] mprj_dat_i_core,
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output mprj_ack_i_core,
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input mprj_iena_wb, // Enable wishbone from user project
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// All signal in/out directions are the reverse of the signal
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// names at the buffer intrface.
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output [127:0] la_data_in_mprj,
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input [127:0] la_data_out_mprj,
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input [127:0] la_oenb_mprj,
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input [127:0] la_iena_mprj,
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input [127:0] la_data_out_core,
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output [127:0] la_data_in_core,
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output [127:0] la_oenb_core,
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input [2:0] user_irq_ena,
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output user_clock,
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output user_clock2,
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output user_reset,
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output mprj_cyc_o_user,
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output mprj_stb_o_user,
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output mprj_we_o_user,
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output [3:0] mprj_sel_o_user,
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output [31:0] mprj_adr_o_user,
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output [31:0] mprj_dat_o_user,
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input [31:0] mprj_dat_i_user,
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input mprj_ack_i_user,
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output [2:0] user_irq,
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output user1_vcc_powergood,
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output user2_vcc_powergood,
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output user1_vdd_powergood,
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output user2_vdd_powergood
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);
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wire [462:0] mprj_logic1;
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wire mprj2_logic1;
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wire mprj_vdd_logic1_h;
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wire mprj2_vdd_logic1_h;
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wire mprj_vdd_logic1;
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wire mprj2_vdd_logic1;
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wire [127:0] la_data_in_mprj_bar;
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wire [2:0] user_irq_bar;
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wire [127:0] la_data_in_enable;
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wire [127:0] la_data_out_enable;
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wire [2:0] user_irq_enable;
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wire wb_in_enable;
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wire [31:0] mprj_dat_i_core_bar;
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wire mprj_ack_i_core_bar;
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mprj_logic_high mprj_logic_high_inst (
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`ifdef USE_POWER_PINS
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.vccd1(vccd1),
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.vssd1(vssd1),
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`endif
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.HI(mprj_logic1)
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);
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mprj2_logic_high mprj2_logic_high_inst (
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`ifdef USE_POWER_PINS
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.vccd2(vccd2),
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.vssd2(vssd2),
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`endif
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.HI(mprj2_logic1)
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);
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// Logic high in the VDDA (3.3V) domains
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mgmt_protect_hv powergood_check (
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`ifdef USE_POWER_PINS
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.vccd(vccd),
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.vssd(vssd),
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.vdda1(vdda1),
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.vssa1(vssa1),
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.vdda2(vdda2),
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.vssa2(vssa2),
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`endif
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.mprj_vdd_logic1(mprj_vdd_logic1),
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.mprj2_vdd_logic1(mprj2_vdd_logic1)
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);
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// Buffering from the user side to the management side.
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// NOTE: This is intended to be better protected, by a full
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// chain of an lv-to-hv buffer followed by an hv-to-lv buffer.
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// This serves as a placeholder until that configuration is
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// checked and characterized. The function below forces the
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// data input to the management core to be a solid logic 0 when
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// the user project is powered down.
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assign la_data_in_enable = la_iena_mprj & mprj_logic1[457:330];
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sky130_fd_sc_hd__nand2_4 user_to_mprj_in_gates [127:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Y(la_data_in_mprj_bar),
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.A(la_data_out_core), // may be floating
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.B(la_data_in_enable)
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);
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assign la_data_in_mprj = ~la_data_in_mprj_bar;
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// Protection, similar to the above, for the three user IRQ lines
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assign user_irq_enable = user_irq_ena & mprj_logic1[460:458];
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sky130_fd_sc_hd__nand2_4 user_irq_gates [2:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Y(user_irq_bar),
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.A(user_irq_core), // may be floating
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.B(user_irq_enable)
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);
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assign user_irq = ~user_irq_bar;
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// Protection, similar to the above, for the return
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// signals from user area to managment on the wishbone bus
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assign wb_in_enable = mprj_iena_wb & mprj_logic1[462];
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sky130_fd_sc_hd__nand2_4 user_wb_dat_gates [31:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Y(mprj_dat_i_core_bar),
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.A(mprj_dat_i_user), // may be floating
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.B(wb_in_enable)
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);
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assign mprj_dat_i_core = ~mprj_dat_i_core_bar;
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sky130_fd_sc_hd__nand2_4 user_wb_ack_gate (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Y(mprj_ack_i_core_bar),
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.A(mprj_ack_i_user), // may be floating
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.B(wb_in_enable)
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);
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assign mprj_ack_i_core = ~mprj_ack_i_core_bar;
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// The remaining circuitry guards against the management
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// SoC dumping current into the user project area when
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// the user project area is powered down.
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assign user_reset = (~caravel_rstn) & mprj_logic1[0];
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assign user_clock = caravel_clk & mprj_logic1[1];
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assign user_clock2 = caravel_clk2 & mprj_logic1[2];
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assign mprj_cyc_o_user = mprj_cyc_o_core & mprj_logic1[3];
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assign mprj_stb_o_user = mprj_stb_o_core & mprj_logic1[4];
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assign mprj_we_o_user = mprj_we_o_core & mprj_logic1[5];
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assign mprj_sel_o_user = mprj_sel_o_core & mprj_logic1[9:6];
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assign mprj_adr_o_user = mprj_adr_o_core & mprj_logic1[41:10];
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assign mprj_dat_o_user = mprj_dat_o_core & mprj_logic1[73:42];
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/* Project data out from the managment side to the user project */
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/* area when the user project is powered down. */
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assign la_data_out_enable = (~la_oenb_mprj) & mprj_logic1[201:74];
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assign la_data_in_core = la_data_out_mprj & la_data_out_enable;
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/* Project data out enable (bar) from the managment side to the */
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/* user project area when the user project is powered down. */
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assign la_oenb_core = la_oenb_mprj & mprj_logic1[329:202];
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/* The conb cell output is a resistive connection directly to */
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/* the power supply, so when returning the user1_powergood */
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/* signal, make sure that it is buffered properly. */
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assign user1_vcc_powergood = mprj_logic1[461];
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assign user2_vcc_powergood = mprj2_logic1;
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assign user1_vdd_powergood = mprj_vdd_logic1;
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assign user2_vdd_powergood = mprj2_vdd_logic1;
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endmodule
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`default_nettype wire
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