mirror of https://github.com/efabless/caravel.git
63 lines
2.0 KiB
Verilog
63 lines
2.0 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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// This module represents an unprogrammed set of GPIO pad default
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// values that is configured with via programming on the chip top
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// level. This value is passed as a set of parameters (formerly
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// part of gpio_control_block.v).
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module gpio_defaults_block #(
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// Parameterized initial startup state of the pad. The default
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// parameters if unspecified is for the pad to be a user input
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// with no pull-up or pull-down, so that it is disconnected
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// from the outside world. See defs.h for configuration word
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// definitions.
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parameter GPIO_CONFIG_INIT = 13'h0402
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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output [12:0] gpio_defaults
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);
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wire [12:0] gpio_defaults_high;
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wire [12:0] gpio_defaults_low;
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// For the mask revision input, use an array of digital constant logic cells
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sky130_fd_sc_hd__conb_1 gpio_default_value [12:0] (
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`ifdef USE_POWER_PINS
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.VPWR(VPWR),
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.VPB(VPWR),
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.VNB(VGND),
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.VGND(VGND),
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`endif
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.HI(gpio_defaults_high),
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.LO(gpio_defaults_low)
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);
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genvar i;
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generate
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for (i = 0; i < 13; i = i+1) begin
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assign gpio_defaults[i] = (GPIO_CONFIG_INIT & (13'h0001 << i)) ?
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gpio_defaults_high[i] : gpio_defaults_low[i];
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end
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endgenerate
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endmodule
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`default_nettype wire
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