mirror of https://github.com/efabless/caravel.git
352 lines
13 KiB
Verilog
352 lines
13 KiB
Verilog
`ifdef SIM
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`default_nettype wire
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`endif
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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/*--------------------------------------------------------------*/
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/* caravel, a project harness for the Google/SkyWater sky130 */
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/* fabrication process and open source PDK */
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/* */
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/* Copyright 2020 efabless, Inc. */
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/* Written by Tim Edwards, December 2019 */
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/* and Mohamed Shalan, August 2020 */
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/* This file is open source hardware released under the */
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/* Apache 2.0 license. See file LICENSE. */
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/* */
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/* Updated 10/15/2021: Revised using the housekeeping module */
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/* from housekeeping.v (refactoring a number of functions from */
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/* the management SoC). */
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/* */
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/*--------------------------------------------------------------*/
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module caravel (
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// All top-level I/O are package-facing pins
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inout vddio, // Common 3.3V padframe/ESD power
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inout vddio_2, // Common 3.3V padframe/ESD power
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inout vssio, // Common padframe/ESD ground
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inout vssio_2, // Common padframe/ESD ground
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inout vdda, // Management 3.3V power
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inout vssa, // Common analog ground
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inout vccd, // Management/Common 1.8V power
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inout vssd, // Common digital ground
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inout vdda1, // User area 1 3.3V power
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inout vdda1_2, // User area 1 3.3V power
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inout vdda2, // User area 2 3.3V power
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inout vssa1, // User area 1 analog ground
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inout vssa1_2, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V power
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inout vccd2, // User area 2 1.8V power
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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inout gpio, // Used for external LDO control
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inout [`MPRJ_IO_PADS-1:0] mprj_io,
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input clock, // CMOS core clock input, not a crystal
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input resetb, // Reset input (Active Low)
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// Note that only two flash data pins are dedicated to the
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// management SoC wrapper. The management SoC exports the
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// quad SPI mode status to make use of the top two mprj_io
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// pins for io2 and io3.
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output flash_csb,
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output flash_clk,
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inout flash_io0,
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inout flash_io1
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);
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//------------------------------------------------------------
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// This value is uniquely defined for each user project.
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//------------------------------------------------------------
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parameter USER_PROJECT_ID = 32'h00000000;
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/*
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*--------------------------------------------------------------------
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* These pins are overlaid on mprj_io space. They have the function
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* below when the management processor is in reset, or in the default
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* configuration. They are assigned to uses in the user space by the
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* configuration program running off of the SPI flash. Note that even
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* when the user has taken control of these pins, they can be restored
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* to the original use by setting the resetb pin low. The SPI pins and
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* UART pins can be connected directly to an FTDI chip as long as the
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* FTDI chip sets these lines to high impedence (input function) at
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* all times except when holding the chip in reset.
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*
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* JTAG = mprj_io[0] (inout)
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* SDO = mprj_io[1] (output)
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* SDI = mprj_io[2] (input)
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* CSB = mprj_io[3] (input)
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* SCK = mprj_io[4] (input)
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* ser_rx = mprj_io[5] (input)
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* ser_tx = mprj_io[6] (output)
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* irq = mprj_io[7] (input)
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*
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* spi_sck = mprj_io[32] (output)
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* spi_csb = mprj_io[33] (output)
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* spi_sdi = mprj_io[34] (input)
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* spi_sdo = mprj_io[35] (output)
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* flash_io2 = mprj_io[36] (inout)
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* flash_io3 = mprj_io[37] (inout)
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*
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* These pins are reserved for any project that wants to incorporate
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* its own processor and flash controller. While a user project can
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* technically use any available I/O pins for the purpose, these
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* four pins connect to a pass-through mode from the SPI slave (pins
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* 1-4 above) so that any SPI flash connected to these specific pins
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* can be accessed through the SPI slave even when the processor is in
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* reset.
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*
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* user_flash_csb = mprj_io[8]
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* user_flash_sck = mprj_io[9]
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* user_flash_io0 = mprj_io[10]
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* user_flash_io1 = mprj_io[11]
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*
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*--------------------------------------------------------------------
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*/
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// One-bit GPIO dedicated to management SoC (outside of user control)
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wire gpio_out_core;
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wire gpio_in_core;
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wire gpio_mode0_core;
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wire gpio_mode1_core;
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wire gpio_outenb_core;
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wire gpio_inenb_core;
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// User Project Control (pad-facing)
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wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
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wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_one;
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// User Project Control (user-facing)
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wire [`MPRJ_IO_PADS-10:0] user_analog_io;
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// User Project Control management I/O
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// There are two types of GPIO connections:
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// (1) Full Bidirectional: Management connects to in, out, and oeb
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// Uses: JTAG and SDO
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// (2) Selectable bidirectional: Management connects to in and out,
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// which are tied together. oeb is grounded (oeb from the
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// configuration is used)
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// SDI = mprj_io[2] (input)
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// CSB = mprj_io[3] (input)
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// SCK = mprj_io[4] (input)
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// ser_rx = mprj_io[5] (input)
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// ser_tx = mprj_io[6] (output)
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// irq = mprj_io[7] (input)
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wire clock_core;
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// Power-on-reset signal. The reset pad generates the sense-inverted
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// reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
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// derived.
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wire porb_h;
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wire porb_l;
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wire por_l;
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wire rstb_h;
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// Flash SPI communication (
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wire flash_clk_frame;
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wire flash_csb_frame;
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wire flash_clk_oeb, flash_csb_oeb;
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wire flash_clk_ieb, flash_csb_ieb;
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wire flash_io0_oeb, flash_io1_oeb;
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wire flash_io0_ieb, flash_io1_ieb;
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wire flash_io0_do, flash_io1_do;
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wire flash_io0_di, flash_io1_di;
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wire vddio_core;
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wire vssio_core;
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wire vdda_core;
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wire vssa_core;
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wire vccd_core;
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wire vssd_core;
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wire vdda1_core;
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wire vdda2_core;
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wire vssa1_core;
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wire vssa2_core;
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wire vccd1_core;
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wire vccd2_core;
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wire vssd1_core;
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wire vssd2_core;
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chip_io padframe (
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`ifndef TOP_ROUTING
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// Package Pins
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.vddio_pad(vddio), // Common padframe/ESD supply
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.vddio_pad2(vddio_2),
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.vssio_pad(vssio), // Common padframe/ESD ground
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.vssio_pad2(vssio_2),
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.vccd_pad(vccd), // Common 1.8V supply
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.vssd_pad(vssd), // Common digital ground
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.vdda_pad(vdda), // Management analog 3.3V supply
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.vssa_pad(vssa), // Management analog ground
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.vdda1_pad(vdda1), // User area 1 3.3V supply
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.vdda1_pad2(vdda1_2),
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.vdda2_pad(vdda2), // User area 2 3.3V supply
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.vssa1_pad(vssa1), // User area 1 analog ground
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.vssa1_pad2(vssa1_2),
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.vssa2_pad(vssa2), // User area 2 analog ground
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.vccd1_pad(vccd1), // User area 1 1.8V supply
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.vccd2_pad(vccd2), // User area 2 1.8V supply
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.vssd1_pad(vssd1), // User area 1 digital ground
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.vssd2_pad(vssd2), // User area 2 digital ground
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.vddio(vddio_core),
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.vssio(vssio_core),
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.vdda(vdda_core),
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.vssa(vssa_core),
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.vccd(vccd_core),
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.vssd(vssd_core),
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.vdda1(vdda1_core),
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.vdda2(vdda2_core),
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.vssa1(vssa1_core),
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.vssa2(vssa2_core),
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.vccd1(vccd1_core),
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.vccd2(vccd2_core),
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.vssd1(vssd1_core),
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.vssd2(vssd2_core),
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// Core Side Pins
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.gpio(gpio),
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.mprj_io(mprj_io),
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.clock(clock),
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.resetb(resetb),
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.flash_csb(flash_csb),
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.flash_clk(flash_clk),
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.flash_io0(flash_io0),
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.flash_io1(flash_io1),
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`endif
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// SoC Core Interface
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.porb_h(porb_h),
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.por(por_l),
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.resetb_core_h(rstb_h),
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.clock_core(clock_core),
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.gpio_out_core(gpio_out_core),
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.gpio_in_core(gpio_in_core),
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.gpio_mode0_core(gpio_mode0_core),
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.gpio_mode1_core(gpio_mode1_core),
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.gpio_outenb_core(gpio_outenb_core),
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.gpio_inenb_core(gpio_inenb_core),
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.flash_csb_core(flash_csb_frame),
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.flash_clk_core(flash_clk_frame),
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.flash_csb_oeb_core(flash_csb_oeb),
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.flash_clk_oeb_core(flash_clk_oeb),
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.flash_io0_oeb_core(flash_io0_oeb),
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.flash_io1_oeb_core(flash_io1_oeb),
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.flash_io0_ieb_core(flash_io0_ieb),
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.flash_io1_ieb_core(flash_io1_ieb),
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.flash_io0_do_core(flash_io0_do),
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.flash_io1_do_core(flash_io1_do),
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.flash_io0_di_core(flash_io0_di),
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.flash_io1_di_core(flash_io1_di),
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.mprj_io_one(mprj_io_one),
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.mprj_io_in(mprj_io_in),
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.mprj_io_out(mprj_io_out),
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.mprj_io_oeb(mprj_io_oeb),
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.mprj_io_inp_dis(mprj_io_inp_dis),
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.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
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.mprj_io_vtrip_sel(mprj_io_vtrip_sel),
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.mprj_io_slow_sel(mprj_io_slow_sel),
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.mprj_io_holdover(mprj_io_holdover),
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.mprj_io_analog_en(mprj_io_analog_en),
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.mprj_io_analog_sel(mprj_io_analog_sel),
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.mprj_io_analog_pol(mprj_io_analog_pol),
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.mprj_io_dm(mprj_io_dm),
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.mprj_analog_io(user_analog_io)
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);
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caravel_core chip_core (
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// All top-level I/O are package-facing pins
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`ifdef USE_POWER_PINS
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.vddio(vddio_core), // Common 3.3V padframe/ESD power
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.vssio(vssio_core), // Common padframe/ESD ground
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.vdda (vdda_core), // Management 3.3V power
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.vssa (vssa_core), // Common analog ground
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.vccd (vccd_core), // Management/Common 1.8V power
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.vssd (vssd_core), // Common digital ground
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.vdda1(vdda1_core), // User area 1 3.3V power
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.vdda2(vdda2_core), // User area 2 3.3V power
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.vssa1(vssa1_core), // User area 1 analog ground
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.vssa2(vssa2_core), // User area 2 analog ground
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.vccd1(vccd1_core), // User area 1 1.8V power
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.vccd2(vccd2_core), // User area 2 1.8V power
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.vssd1(vssd1_core), // User area 1 digital ground
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.vssd2(vssd2_core), // User area 2 digital ground
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`endif
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// SoC Core Interface
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.porb_h(porb_h),
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.por_l(por_l),
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.rstb_h(rstb_h),
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.clock_core(clock_core),
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.gpio_out_core(gpio_out_core),
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.gpio_in_core(gpio_in_core),
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.gpio_mode0_core(gpio_mode0_core),
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.gpio_mode1_core(gpio_mode1_core),
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.gpio_outenb_core(gpio_outenb_core),
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.gpio_inenb_core(gpio_inenb_core),
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// Flash SPI communication
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.flash_csb_frame(flash_csb_frame),
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.flash_clk_frame(flash_clk_frame),
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.flash_csb_oeb(flash_csb_oeb),
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.flash_clk_oeb(flash_clk_oeb),
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.flash_io0_oeb(flash_io0_oeb),
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.flash_io1_oeb(flash_io1_oeb),
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.flash_io0_ieb(flash_io0_ieb),
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.flash_io1_ieb(flash_io1_ieb),
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.flash_io0_do(flash_io0_do),
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.flash_io1_do(flash_io1_do),
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.flash_io0_di(flash_io0_di),
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.flash_io1_di(flash_io1_di),
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// User project IOs
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.mprj_io_in(mprj_io_in),
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.mprj_io_out(mprj_io_out),
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.mprj_io_oeb(mprj_io_oeb),
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.mprj_io_inp_dis(mprj_io_inp_dis),
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.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
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.mprj_io_vtrip_sel(mprj_io_vtrip_sel),
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.mprj_io_slow_sel(mprj_io_slow_sel),
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.mprj_io_holdover(mprj_io_holdover),
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.mprj_io_analog_en(mprj_io_analog_en),
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.mprj_io_analog_sel(mprj_io_analog_sel),
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.mprj_io_analog_pol(mprj_io_analog_pol),
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.mprj_io_dm(mprj_io_dm),
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// Loopbacks to constant value 1 in the 1.8V domain
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.mprj_io_one(mprj_io_one),
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// User project direct access to gpio pad connections for analog
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// (all but the lowest-numbered 7 pads)
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.mprj_analog_io(user_analog_io)
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);
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endmodule
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// `default_nettype wire
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