mirror of https://github.com/efabless/caravel.git
45 lines
2.1 KiB
Verilog
45 lines
2.1 KiB
Verilog
// module that has registers used for debug
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module debug_regs (
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output reg wbs_ack_o,
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output reg [31:0] wbs_dat_o);
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reg [31:0] debug_reg_1;
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reg [31:0] debug_reg_2;
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// write
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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if (wb_rst_i) begin
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debug_reg_1 <=0;
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debug_reg_2 <=0;
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wbs_dat_o <=0;
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wbs_ack_o <=0;
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end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8))begin // write
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// write to reg1
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debug_reg_1[7:0] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_1[7:0];
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debug_reg_1[15:8] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_1[15:8];
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debug_reg_1[23:16] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_1[23:16];
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debug_reg_1[31:24] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_1[31:24];
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// write to reg2
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debug_reg_2[7:0] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_2[7:0];
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debug_reg_2[15:8] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_2[15:8];
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debug_reg_2[23:16] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_2[23:16];
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debug_reg_2[31:24] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24];
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wbs_ack_o <= 1;
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end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8)) begin // read
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wbs_dat_o <= ((wbs_adr_i[3:0]==4'hC)) ? debug_reg_2 : debug_reg_1;
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wbs_ack_o <= 1;
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end else begin
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wbs_ack_o <= 0;
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wbs_dat_o <= 0;
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end
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end
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endmodule
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`default_nettype wire |