Tim Edwards 842200b7ec Changed the memory map to move the 2e and 2f wishbone domains into ... the 26 domain (now dedicated to the housekeeping module), with 2e0... now 261... and 2f0... now 262... Although this is not strictly backwards-compatible, the addresses in defs.h have been modified so that C code remains valid with a recompile.		2021-10-16 17:58:36 -04:00
..
__uprj_analog_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__uprj_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__user_analog_project_wrapper.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__user_project_wrapper.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravan.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravan_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravel.v	Reinstated the logic analyzer as a standard interface for the	2021-10-16 17:42:24 -04:00
caravel_clocking.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravel_netlists.v	First major update; current code passes syntax checks in iverilog	2021-10-15 21:49:49 -04:00
caravel_openframe.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
chip_io.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
chip_io_alt.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
clock_div.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
defines.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
digital_pll.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
digital_pll_controller.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
gpio_control_block.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
gpio_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
housekeeping.v	Changed the memory map to move the 2e and 2f wishbone domains into	2021-10-16 17:58:36 -04:00
housekeeping_spi.v	First major update; current code passes syntax checks in iverilog	2021-10-15 21:49:49 -04:00
mgmt_protect.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mgmt_protect_hv.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj2_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj_io.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
pads.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
ring_osc2x13.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
simple_por.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
user_id_programming.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00