mirror of https://github.com/efabless/caravel.git
60 lines
2.0 KiB
Python
60 lines
2.0 KiB
Python
import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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from interfaces.cpu import RiskV
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from interfaces.defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from interfaces.caravel import GPIO_MODE
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reg = Regs()
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@cocotb.test()
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@repot_test
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async def mem_dff2(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=1426536)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start mem stress test")
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pass_list = [0x1B]
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fail_list = [0x1E]
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reg1 =0 # buffer
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while True:
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if cpu.read_debug_reg1() == 0xFF: # test finish
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break
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if reg1 != cpu.read_debug_reg1():
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reg1 = cpu.read_debug_reg1()
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if reg1 in pass_list: # pass phase
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cocotb.log.info(f"[TEST] pass writing and reading all dff2 memory ")
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break
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elif reg1 in fail_list: # pass phase
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cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")
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break
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await ClockCycles(caravelEnv.clk,100)
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@cocotb.test()
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@repot_test
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async def mem_dff(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=2378120)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start mem stress test")
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pass_list = [0x1B]
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fail_list = [0x1E]
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reg1 =0 # buffer
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while True:
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if reg1 != cpu.read_debug_reg1():
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reg1 = cpu.read_debug_reg1()
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if reg1 in pass_list: # pass phase
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cocotb.log.info(f"[TEST] pass writing and reading all dff memory ")
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break
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elif reg1 in fail_list: # pass phase
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cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")
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break
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await ClockCycles(caravelEnv.clk,100)
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