mirror of https://github.com/efabless/caravel.git
158 lines
4.7 KiB
Tcl
158 lines
4.7 KiB
Tcl
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set ::env(DESIGN_NAME) gpio_control_block
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set ::env(VERILOG_FILES) "\
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$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
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$::env(DESIGN_DIR)/../../verilog/rtl/gpio_control_block.v"
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set ::env(PL_TARGET_DENSITY) 0.9
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set ::env(CLOCK_PORT) "serial_clock"
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set ::env(FP_DEF_TEMPLATE) "$::env(DESIGN_DIR)/template/gpio_control_block.def"
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# This needs to be half the mgmt_core clock frequency
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set ::env(CLOCK_PERIOD) "50"
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set ::env(VDD_NETS) "vccd vccd1"
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set ::env(GND_NETS) "vssd vssd1"
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set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
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## Synthesis
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
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set ::env(SYNTH_STRATEGY) "AREA 0"
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## Floorplan
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 170 65"
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set ::env(RIGHT_MARGIN_MULT) 256
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set ::env(LEFT_MARGIN_MULT) 10
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set ::env(TOP_MARGIN_MULT) 1
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set ::env(BOTTOM_MARGIN_MULT) 1
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set ::env(DPL_CELL_PADDING) 0
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set ::env(GPL_CELL_PADDING) 0
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set ::env(DIODE_PADDING) 0
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## PDN
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set ::env(FP_PDN_MACRO_HOOKS) "\
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gpio_logic_high vccd1 vssd1 vccd1 vssd1"
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set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
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set ::env(FP_PDN_AUTO_ADJUST) 0
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set ::env(FP_PDN_VWIDTH) 1.6
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set ::env(FP_PDN_HWIDTH) 1.6
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set ::env(FP_PDN_HORIZONTAL_HALO) 0
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set ::env(FP_PDN_VERTICAL_HALO) 0
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set ::env(FP_PDN_CHECK_NODES) 0
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# these PDN vars are mostly hard coded in the custom ./pdn.tcl file
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# keeping them in case openlane depends on the variable definition
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set ::env(FP_PDN_HOFFSET) 1.5
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set ::env(FP_PDN_VOFFSET) 9.0
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set ::env(FP_PDN_HPITCH) 20
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set ::env(FP_PDN_VPITCH) 25
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set ::env(FP_PDN_VSPACING) 3.4
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set ::env(FP_PDN_HSPACING) 3.4
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## Placement
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set ::env(PL_TARGET_DENSITY) 0.9
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# for some reason resizer is leaving a floating net after running repair_tie_fanout command
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set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0
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# mgmt_gpio_in is driven by a tristate cell
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# set ::env(DONT_BUFFER_PORTS) "mgmt_gpio_in"
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## Routing
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set ::env(GRT_MINLAYER) 2
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set ::env(GRT_MAXLAYER) 4
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set ::env(GRT_ADJUSTMENT) 0.05
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# Add obstructions on the areas that will lie underneath the padframe
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set ::env(GRT_OBS) "\
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li1 0 0 16.79500 30.02500,
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li1 0 29.96500 4.26500 65.07000,
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li1 4.21500 57.40500 49.81500 64.93000,
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li1 16.83000 0 49.41000 5.24000,
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li1 49.000 0 169.81000 64.84500,
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met5 50 0 170 65,
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met4 49 0 170 65,
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met2 120 0 170 65,
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met1 120 0 170 65"
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) 4
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set ::env(FP_TAP_HORIZONTAL_HALO) {2}
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set ::env(FP_TAP_VERTICAL_HALO) {2}
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## Internal macros
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set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$::env(DESIGN_DIR)/../../verilog/rtl/gpio_logic_high.v"
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set ::env(EXTRA_LEFS) "\
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$::env(DESIGN_DIR)/../../lef/gpio_logic_high.lef"
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set ::env(EXTRA_GDS_FILES) "\
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$::env(DESIGN_DIR)/../../gds/gpio_logic_high.gds"
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
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#Placement
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
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#Post cts
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 1
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set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 1
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set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 1
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set ::env(PL_RESIZER_MAX_CAP_MARGIN) 1
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set ::env(CLOCK_TREE_SYNTH) 1
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set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/template/gpio_control_block.def
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set ::env(SYNTH_BUFFERING) 0
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set ::env(SYNTH_SIZING) 0
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# 0.07 ns 70 ps
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# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.07
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# set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
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# set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2
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set ::env(QUIT_ON_MAGIC_DRC) 1
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set ::env(QUIT_ON_LVS_ERROR) 1
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set ::env(SYNTH_EXTRA_MAPPING_FILE) $::env(DESIGN_DIR)/yosys_mapping.v
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set ::env(DECAP_CELL) {sky130_fd_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
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set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/drc_exclude_list.txt
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set ::env(DRC_EXCLUDE_CELL_LIST_OPT) $::env(DESIGN_DIR)/drc_exclude_list.txt
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set ::env(RSZ_DONT_TOUCH) "user_gpio_out user_gpio_oeb serial_clock_out serial_load_out gpio_defaults*"
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set ::env(FP_PDN_SKIPTRIM) 1
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