mirror of https://github.com/efabless/caravel.git
94 lines
2.2 KiB
Verilog
94 lines
2.2 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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`timescale 1 ns / 1 ps
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module simple_por(
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`ifdef USE_POWER_PINS
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inout vdd3v3,
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inout vdd1v8,
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inout vss3v3,
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inout vss1v8,
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`endif
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output porb_h,
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output porb_l,
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output por_l
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);
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wire mid;
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reg inode;
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// This is a behavioral model! Actual circuit is a resitor dumping
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// current (slowly) from vdd3v3 onto a capacitor, and this fed into
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// two schmitt triggers for strong hysteresis/glitch tolerance.
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initial begin
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inode <= 1'b0;
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end
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// Emulate current source on capacitor as a 500ns delay either up or
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// down. Note that this is sped way up for verilog simulation; the
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// actual circuit is set to a 15ms delay.
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always @(posedge vdd3v3) begin
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#500 inode <= 1'b1;
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end
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always @(negedge vdd3v3) begin
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#500 inode <= 1'b0;
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end
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// Instantiate two shmitt trigger buffers in series
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sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
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`ifdef USE_POWER_PINS
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.VPWR(vdd3v3),
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.VGND(vss3v3),
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.VPB(vdd3v3),
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.VNB(vss3v3),
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`endif
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.A(inode),
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.X(mid)
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);
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sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
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`ifdef USE_POWER_PINS
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.VPWR(vdd3v3),
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.VGND(vss3v3),
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.VPB(vdd3v3),
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.VNB(vss3v3),
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`endif
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.A(mid),
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.X(porb_h)
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);
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sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
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`ifdef USE_POWER_PINS
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.VPWR(vdd3v3),
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.VPB(vdd3v3),
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.LVPWR(vdd1v8),
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.VNB(vss3v3),
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.VGND(vss3v3),
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`endif
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.A(porb_h),
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.X(porb_l)
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);
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// since this is behavioral anyway, but this should be
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// replaced by a proper inverter
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assign por_l = ~porb_l;
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endmodule
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`default_nettype wire
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