caravel/verilog/dv/wb_utests/sysctrl_wb
Tim Edwards 00e0a5f603 Corrected the two failing testbenches (which needed fixing because
the implementation of the housekeeping module changed the addresses
of the signals being exercised).
2021-10-28 22:20:46 -04:00
..
Makefile Added back wishbone verification tests, specifically those related 2021-10-28 17:26:06 -04:00
sysctrl_wb_tb.v Corrected the two failing testbenches (which needed fixing because 2021-10-28 22:20:46 -04:00