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caravel/lef/caravel_power_routing.lef

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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO caravel_power_routing
CLASS BLOCK ;
FOREIGN caravel_power_routing ;
ORIGIN 0.000 0.000 ;
SIZE 3588.000 BY 5188.000 ;
PIN vccd_core
PORT
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RECT 197.280 341.280 229.220 364.500 ;
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END
END vccd_core
PIN vssd_core
PORT
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LAYER met5 ;
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RECT 234.180 213.940 2956.980 232.940 ;
END
END vssd_core
PIN vccd2_core
PORT
LAYER met4 ;
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RECT 306.910 1339.590 326.260 1342.690 ;
RECT 323.160 1207.330 326.260 1339.590 ;
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RECT 220.980 1172.330 234.010 1192.330 ;
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LAYER via4 ;
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RECT 324.065 1202.450 325.245 1203.630 ;
RECT 324.065 1200.850 325.245 1202.030 ;
RECT 324.065 1199.250 325.245 1200.430 ;
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RECT 1025.250 1204.085 1026.430 1205.265 ;
RECT 1025.250 1202.485 1026.430 1203.665 ;
RECT 1025.250 1200.885 1026.430 1202.065 ;
RECT 1025.250 1199.285 1026.430 1200.465 ;
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LAYER met5 ;
RECT 221.270 1172.660 233.590 1206.790 ;
RECT 281.390 1192.330 3266.530 1207.330 ;
END
END vccd2_core
PIN vssd2_core
PORT
LAYER met4 ;
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RECT 302.110 1334.790 321.460 1337.890 ;
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LAYER via4 ;
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RECT 319.315 1212.870 320.495 1214.050 ;
RECT 995.550 1225.685 996.730 1226.865 ;
RECT 995.550 1224.085 996.730 1225.265 ;
RECT 995.550 1222.485 996.730 1223.665 ;
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LAYER met5 ;
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RECT 281.390 1212.330 3271.110 1227.330 ;
END
END vssd2_core
PIN vdda2_core
PORT
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RECT 199.620 2415.495 261.460 2439.395 ;
LAYER via3 ;
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LAYER met4 ;
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LAYER met5 ;
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END
END vdda2_core
PIN vssa2_core
PORT
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END
END vssa2_core
PIN vssd1_core
PORT
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END
END vssd1_core
PIN vccd1_core
PORT
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RECT 30.425 1025.740 34.900 1025.850 ;
RECT 30.425 1024.140 43.070 1025.740 ;
RECT 30.425 1024.040 34.900 1024.140 ;
END
END vccd1_core
PIN vssa1_core
PORT
LAYER met3 ;
RECT 2878.500 4975.160 2902.395 4988.390 ;
RECT 2928.390 4975.160 2952.290 4988.390 ;
RECT 3319.570 2128.740 3388.560 2152.505 ;
RECT 3319.570 2127.810 3335.550 2128.740 ;
RECT 3319.570 2078.710 3388.560 2102.610 ;
LAYER via3 ;
RECT 2879.070 4975.715 2901.790 4985.235 ;
RECT 2928.920 4975.745 2951.640 4985.265 ;
RECT 3320.725 2128.425 3332.645 2151.945 ;
RECT 3320.640 2079.435 3332.560 2102.155 ;
LAYER met4 ;
RECT 2878.400 4953.940 2902.390 4985.650 ;
RECT 2928.350 4954.010 2952.340 4985.720 ;
RECT 3320.040 2127.860 3333.060 2152.450 ;
RECT 3320.090 2078.800 3333.170 2102.620 ;
RECT 292.510 1332.040 295.610 1364.960 ;
RECT 1953.860 1332.370 1957.790 1347.350 ;
RECT 2029.110 1332.370 2033.040 1347.350 ;
RECT 1956.870 1311.040 1957.770 1332.370 ;
RECT 2032.120 1311.040 2033.020 1332.370 ;
RECT 3277.090 1331.930 3280.190 1365.020 ;
LAYER via4 ;
RECT 2879.375 4955.105 2901.355 4965.885 ;
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RECT 3321.210 2079.805 3331.990 2101.785 ;
RECT 293.445 1345.640 294.625 1346.820 ;
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RECT 293.445 1340.840 294.625 1342.020 ;
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RECT 293.445 1337.640 294.625 1338.820 ;
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RECT 293.445 1334.440 294.625 1335.620 ;
RECT 293.445 1332.840 294.625 1334.020 ;
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END
END vssa1_core
PIN vdda1_core
PORT
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RECT 312.670 1312.330 3349.100 1327.330 ;
END
END vdda1_core
OBS
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RECT 3546.270 859.060 3558.935 859.140 ;
RECT 3546.270 859.040 3558.930 859.060 ;
RECT 3489.650 855.400 3493.975 855.460 ;
RECT 3489.650 853.800 3502.060 855.400 ;
RECT 3489.650 853.690 3493.975 853.800 ;
RECT 3548.560 852.190 3552.740 852.280 ;
RECT 3546.110 850.590 3552.740 852.190 ;
RECT 3548.560 850.480 3552.740 850.590 ;
RECT 3495.650 846.950 3499.975 847.055 ;
RECT 3495.650 845.350 3502.060 846.950 ;
RECT 3495.650 845.285 3499.975 845.350 ;
RECT 3554.525 843.740 3558.710 843.820 ;
RECT 3546.110 842.140 3558.710 843.740 ;
RECT 3554.525 842.045 3558.710 842.140 ;
RECT 3489.680 838.500 3494.005 838.600 ;
RECT 3489.680 836.900 3502.060 838.500 ;
RECT 3489.680 836.830 3494.005 836.900 ;
RECT 3377.040 693.240 3382.450 698.730 ;
RECT 3358.510 685.150 3363.920 690.640 ;
RECT 3495.790 678.780 3499.920 678.840 ;
RECT 3495.790 677.180 3517.630 678.780 ;
RECT 3495.790 677.125 3499.920 677.180 ;
RECT 3489.735 675.280 3493.865 675.355 ;
RECT 3489.570 673.680 3517.630 675.280 ;
RECT 3489.735 673.640 3493.865 673.680 ;
RECT 3548.580 659.990 3552.765 660.075 ;
RECT 3546.270 658.390 3552.880 659.990 ;
RECT 3548.580 658.300 3552.765 658.390 ;
RECT 3495.630 654.750 3499.955 654.850 ;
RECT 3495.630 653.150 3502.060 654.750 ;
RECT 3495.630 653.080 3499.955 653.150 ;
RECT 3554.585 651.540 3558.770 651.620 ;
RECT 3546.270 649.940 3558.940 651.540 ;
RECT 3554.585 649.845 3558.770 649.940 ;
RECT 3489.645 646.300 3493.970 646.360 ;
RECT 3489.645 644.700 3502.060 646.300 ;
RECT 3489.645 644.590 3493.970 644.700 ;
RECT 3548.555 643.090 3552.740 643.205 ;
RECT 3546.270 641.490 3552.850 643.090 ;
RECT 3548.555 641.430 3552.740 641.490 ;
RECT 3495.745 637.850 3500.070 637.935 ;
RECT 3495.745 636.250 3502.060 637.850 ;
RECT 3495.745 636.165 3500.070 636.250 ;
RECT 3554.530 634.640 3558.940 634.750 ;
RECT 3546.270 633.140 3558.940 634.640 ;
RECT 3546.270 633.060 3558.935 633.140 ;
RECT 3546.270 633.040 3558.930 633.060 ;
RECT 3489.650 629.400 3493.975 629.460 ;
RECT 3489.650 627.800 3502.060 629.400 ;
RECT 3489.650 627.690 3493.975 627.800 ;
RECT 3548.560 626.190 3552.740 626.280 ;
RECT 3546.110 624.590 3552.740 626.190 ;
RECT 3548.560 624.480 3552.740 624.590 ;
RECT 3495.650 620.950 3499.975 621.055 ;
RECT 3495.650 619.350 3502.060 620.950 ;
RECT 3495.650 619.285 3499.975 619.350 ;
RECT 3554.525 617.740 3558.710 617.820 ;
RECT 3546.110 616.140 3558.710 617.740 ;
RECT 3554.525 616.045 3558.710 616.140 ;
RECT 3489.680 612.500 3494.005 612.600 ;
RECT 3489.680 610.900 3502.060 612.500 ;
RECT 3489.680 610.830 3494.005 610.900 ;
END
END caravel_power_routing
END LIBRARY
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