mirror of https://github.com/efabless/caravel.git
196 lines
4.2 KiB
Plaintext
196 lines
4.2 KiB
Plaintext
VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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MACRO caravel_clocking
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CLASS BLOCK ;
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FOREIGN caravel_clocking ;
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ORIGIN 0.000 0.000 ;
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SIZE 80.000 BY 80.000 ;
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PIN VGND
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DIRECTION INPUT ;
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 27.705 10.640 29.305 68.240 ;
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END
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PORT
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LAYER met4 ;
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RECT 50.690 10.640 52.290 68.240 ;
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END
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END VGND
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PIN VPWR
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DIRECTION INPUT ;
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 16.215 10.640 17.815 68.240 ;
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END
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PORT
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LAYER met4 ;
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RECT 39.200 10.640 40.800 68.240 ;
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END
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PORT
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LAYER met4 ;
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RECT 62.185 10.640 63.785 68.240 ;
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END
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END VPWR
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PIN core_clk
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 13.430 76.000 13.710 80.000 ;
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END
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END core_clk
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PIN ext_clk
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 59.890 0.000 60.170 4.000 ;
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END
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END ext_clk
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PIN ext_clk_sel
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 76.000 4.800 80.000 5.400 ;
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END
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END ext_clk_sel
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PIN ext_reset
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 76.000 74.840 80.000 75.440 ;
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END
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END ext_reset
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PIN pll_clk
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 0.000 19.760 4.000 20.360 ;
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END
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END pll_clk
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PIN pll_clk90
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 0.000 59.880 4.000 60.480 ;
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END
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END pll_clk90
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PIN resetb
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 19.870 0.000 20.150 4.000 ;
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END
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END resetb
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PIN resetb_sync
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 66.790 76.000 67.070 80.000 ;
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END
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END resetb_sync
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PIN sel2[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 76.000 44.920 80.000 45.520 ;
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END
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END sel2[0]
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PIN sel2[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 76.000 54.440 80.000 55.040 ;
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END
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END sel2[1]
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PIN sel2[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 76.000 64.640 80.000 65.240 ;
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END
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END sel2[2]
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PIN sel[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 76.000 14.320 80.000 14.920 ;
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END
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END sel[0]
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PIN sel[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 76.000 24.520 80.000 25.120 ;
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END
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END sel[1]
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PIN sel[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 76.000 34.720 80.000 35.320 ;
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END
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END sel[2]
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PIN user_clk
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 40.110 76.000 40.390 80.000 ;
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END
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END user_clk
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OBS
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LAYER li1 ;
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RECT 5.520 5.185 77.135 75.055 ;
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LAYER met1 ;
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RECT 5.520 5.140 77.195 75.100 ;
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LAYER met2 ;
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RECT 7.000 75.720 13.150 76.000 ;
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RECT 13.990 75.720 39.830 76.000 ;
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RECT 40.670 75.720 66.510 76.000 ;
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RECT 67.350 75.720 75.350 76.000 ;
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RECT 7.000 4.280 75.350 75.720 ;
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RECT 7.000 4.000 19.590 4.280 ;
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RECT 20.430 4.000 59.610 4.280 ;
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RECT 60.450 4.000 75.350 4.280 ;
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LAYER met3 ;
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RECT 4.000 74.440 75.600 75.305 ;
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RECT 4.000 65.640 76.000 74.440 ;
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RECT 4.000 64.240 75.600 65.640 ;
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RECT 4.000 60.880 76.000 64.240 ;
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RECT 4.400 59.480 76.000 60.880 ;
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RECT 4.000 55.440 76.000 59.480 ;
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RECT 4.000 54.040 75.600 55.440 ;
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RECT 4.000 45.920 76.000 54.040 ;
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RECT 4.000 44.520 75.600 45.920 ;
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RECT 4.000 35.720 76.000 44.520 ;
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RECT 4.000 34.320 75.600 35.720 ;
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RECT 4.000 25.520 76.000 34.320 ;
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RECT 4.000 24.120 75.600 25.520 ;
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RECT 4.000 20.760 76.000 24.120 ;
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RECT 4.400 19.360 76.000 20.760 ;
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RECT 4.000 15.320 76.000 19.360 ;
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RECT 4.000 13.920 75.600 15.320 ;
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RECT 4.000 5.800 76.000 13.920 ;
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RECT 4.000 4.935 75.600 5.800 ;
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END
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END caravel_clocking
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END LIBRARY
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