caravel/verilog
kareem 712b784e16 reharden!: digital_pll
~ disable or gate
+ add nosynth list file
2022-10-17 12:33:25 -07:00
..
dv Merge pull request #269 from efabless/cocotb 2022-10-17 18:01:24 +02:00
gl reharden!: digital_pll 2022-10-17 12:33:25 -07:00
rtl Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout 2022-10-17 20:50:01 +02:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00