mirror of https://github.com/efabless/caravel.git
62 lines
3.0 KiB
ReStructuredText
Executable File
62 lines
3.0 KiB
ReStructuredText
Executable File
.. raw:: html
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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Introduction
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============
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The Efabless Caravel chip is a ready-to-use test harness for creating designs with the Google/Skywater 130nm Open PDK.
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The Caravel harness comprises of base functions supporting IO, power and configuration as well as drop-in modules for a
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management soc core, and an approximately 2.8mm x 2.8mm open project area for the placement of user IP blocks.
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.. figure:: _static/caravel_floorplan.jpg
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:name: caravel_floorplan
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:alt: Caravel Floorplan
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:align: center
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Caravel floorplan
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The Github Repo could be found here: https://github.com/efabless/caravel/
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The documentation contains the following chapters:
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* :doc:`description` contains the general information about the Efabless Caravel "harness" SoC,
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* :doc:`getting-started` contains the general information about how to use the Efabless Caravel "harness" SoC,
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* :doc:`tool-versioning` contains the tool versions prefered for usage with the current Efabless Caravel "harness" SoC,
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* :doc:`quick-start` contains a guide on how to get quickly started with using Efabless Caravel "harness" SoC without many details,
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* :doc:`caravel-with-openlane` contains information on how to build your user project with OpenLANE inside the Efabless Caravel "harness" SoC,
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* :doc:`pinout` describes the pinout of the SoC,
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* :doc:`gpio` describes GPIO and its registers,
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* :doc:`housekeeping-spi` describes the SPI responder that can be accessed from a remote host,
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* :doc:`qspi-flash` describes the QSPI flash controller,
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* :doc:`external-clock` describes the source external clock for the CPU,
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* :doc:`uart` describes the UART interface,
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* :doc:`spi` describes the SPI configuration,
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* :doc:`counter-timers` describes two counter/timers blocks,
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* :doc:`irq` describes the interrups,
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* :doc:`sram` describes management and storage area SRAM,
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* :doc:`programming` shows how to get started with programming on Caravel chip,
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* :doc:`memory-mapped-io-summary` lists the memory mapped I/O registers by address,
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* :doc:`supplementary-figures` provides supplementary internal structure and die arrangement figures
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* :doc:`maximum-ratings` lists the parameters and their ranges at which the device operates correctly,
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* :doc:`references` contains list of references,
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* :doc:`further-work` lists things to be added to the documentation.
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