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riscv
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caravel
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https://github.com/efabless/caravel.git
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704f19b6c7
caravel
/
verilog
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kareem
704f19b6c7
reharden: caravel
...
~ correct placement for spare_logic_block ~ add changes from buffering macro
2022-10-16 12:56:41 -07:00
..
dv
fix script to not create directory annotation_logs
2022-10-15 02:54:35 -07:00
gl
reharden: caravel
2022-10-16 12:56:41 -07:00
rtl
Once again. . . Rewrote the RTL verilog so that only signals
2022-10-16 12:49:44 -04:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00