Tim Edwards e0a318d2bf Fixed the GL verilog for caravel and caravan to add the two changes ... just made to the RTL verilog and layout, to separate out hk_cyc_o and to hook up the housekeeping user_clock input.		2021-11-30 12:31:07 -05:00
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dv	Update storage testbench to work with one 2K block	2021-11-12 17:14:21 +02:00
gl	Fixed the GL verilog for caravel and caravan to add the two changes	2021-11-30 12:31:07 -05:00
rtl	Updated caravel and caravan layouts to reflect the simple change	2021-11-30 10:05:43 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00